IDT72V805
IDT72V815
IDT72V825
IDT72V835
IDT72V845
3.3 VOLT CMOS DUAL SyncFIFO™
DUAL 256 x 18, DUAL 512 x 18,
DUAL 1,024 x 18, DUAL 2,048 x 18
and DUAL 4,096 x 18
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
• Easily expandable in depth and width
FEATURES:
• Asynchronous or coincident Read and Write Clocks
• Asynchronous or synchronous programmable Almost-Empty
and Almost-Full flags with default settings
• The IDT72V805 is equivalent to two IDT72V205 256 x 18 FIFOs
• The IDT72V815 is equivalent to two IDT72V215 512 x 18 FIFOs
• The IDT72V825 is equivalent to two IDT72V225 1,024 x 18 FIFOs
• The IDT72V835 is equivalent to two IDT72V235 2,048 x 18 FIFOs
• The IDT72V845 is equivalent to two IDT72V245 4,096 x 18 FIFOs
• Offers optimal combination of large capacity (8K), high speed,
design flexibility, and small footprint
• Half-Full flag capability
• Output enable puts output data bus in high-impedance state
• High-performance submicron CMOS technology
• Available in a 128-pin thin quad flatpack (TQFP)
• Industrial temperature range (–40°C to +85°C) is available
• Green parts available, see ordering information
• Ideal for the following applications:
– Network switching
– Two level prioritization of parallel data
– Bidirectional data transfer
– Bus-matching between 18-bit and 36-bit data paths
– Width expansion to 36-bit per package
– Depth expansion to 8,192 words per package
• 10 ns read/write cycle time
• 5V input tolerant
• IDT Standard or First Word Fall Through timing
• Single or double register-buffered Empty and Full Flags
DESCRIPTION:
The IDT72V805/72V815/72V825/72V835/72V845 are dual 18-bit-wide
synchronous (clocked) First-in, First-out (FIFO) memories designed to run
off a 3.3V supply for exceptionally low power consumption. One dual
IDT72V805/72V815/72V825/72V835/72V845deviceisfunctionallyequiva-
lent to two IDT72V205/72V215/72V225/72V235/72V245 FIFOs in a single
package with all associated control, data, and flag lines assigned to
independent pins. These devices are very high-speed, low-power First-In,
FUNCTIONAL BLOCK DIAGRAM
HFA/(WXOA)
FFA/IRA
PAEA
EFA/
ORA
WCLKA
WENA
WCLKB
DA0-DA17
LDA
WENB
DB0-DB17
LDB
PAFA
INPUT
REGISTER
OFFSET
REGISTER
INPUT
REGISTER
OFFSET
REGISTER
FFB/IRB
FLAG
PAFB
WRITE
FLAG
LOGIC
WRITE
EFB/ORB
PAEB
HFB/(WXOB)
RAM
CONTROL
LOGIC
LOGIC
CONTROL
LOGIC
RAM
ARRAY
ARRAY
256 x 18
512 x 18
1,024 x 18
2,048 x 18
4,096 x 18
256 x 18
512 x 18
1,024 x 18
2,048 x 18
4,096 x 18
READ
POINTER
WRITE
POINTER
READ
POINTER
WRITE
POINTER
FLA
WXIA
(HFA)/WXOA
RXIA
READ
CONTROL
LOGIC
READ
CONTROL
LOGIC
EXPANSION
LOGIC
EXPANSION
LOGIC
OUTPUT
REGISTER
OUTPUT
REGISTER
RXOA
RESET
LOGIC
RSA
RESET
LOGIC
RSB
RXOB
RXIB
(HFB)/WXOB
WXIB
FLB
RCLKB
RCLKA
OEB
QA0-QA17
RENB
RENA
OEA
QB0-QB17
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IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology, Inc. TheSyncFIFOisatrademarkofIntegratedDeviceTechnology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
MARCH 2018
1
©
2018 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4295/7