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72V73250 PDF预览

72V73250

更新时间: 2023-12-20 18:45:46
品牌 Logo 应用领域
瑞萨 - RENESAS /
页数 文件大小 规格书
25页 414K
描述
8K x 8K TSI, 16 I/O at 32Mbps, 3.3V

72V73250 数据手册

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3.3 VOLT TIME SLOT INTERCHANGE  
DIGITAL SWITCH  
IDT72V73250  
8,192 x 8,192  
FEATURES:  
DESCRIPTION:  
8K x 8K non-blocking switching at 32.768Mb/s  
16 serial input and output streams  
The IDT72V73250 has a non-blocking switch capacity of 8,192 x 8,192  
channels at 32.768Mb/s. With 16 inputs and 16 outputs, programmable per  
streamcontrol,andavarietyofoperatingmodestheIDT72V73250isdesigned  
fortheTDMtimeslotinterchangefunctionineithervoiceordataapplications.  
Some of the main features of the IDT72V73250 are LOW power 3.3 Volt  
operation, automatic ST-BUS® /GCI sensing, memory block programming,  
simplemicroprocessorinterface, JTAGTestAccessPort(TAP)andperstream  
programmableinputoffsetdelay,variableorconstantthroughputmodes,output  
enable and processor mode.  
Accepts single-bit single-data streams at 32.768Mb/s  
Per-channel Variable Delay Mode for low-latency applications  
Per-channel Constant Delay Mode for frame integrity applications  
Automatic identification of ST-BUS® and GCI bus interfaces  
Automatic frame offset delay measurement  
Per-stream single data frame delay offset programming  
Per-channel high-impedance output control  
Direct microprocessor access to all internal memories  
Memory block programming for quick setup  
IEEE-1149.1 (JTAG) Test Port  
3.3V Power Supply  
Available in 144-pin (20mm x 20mm) Thin Quad Flatpack (TQFP)  
and 144-pin (13mm x 13mm) Plastic Ball Grid Array (PBGA)  
Operating Temperature Range -40°C to +85°C  
The IDT72V73250 is capable of switching up to 8,192 x 8,192 channels  
withoutblocking.Designedtoswitch64Kbit/sPCMorNx64Kbit/sdata,the  
devicemaintainsframeintegrityindataapplicationsandminimizesthroughput  
delay for voice applications on a per-channel basis.  
The16serialinputstreams(RX)oftheIDT72V73250arerunat32.768Mb/s  
allowing512channelsper125μsframe.Thedataratesontheoutputstreams  
(TX) are identicalto those on the input streams(RX).  
FUNCTIONAL BLOCK DIAGRAM  
RESET  
VCC  
GND  
ODE  
TX0  
TX1  
RX0  
RX1  
Data Memory  
MUX  
Receive  
Serial Data  
Streams  
TX7  
Transmit  
Serial Data  
Streams  
TX8/OEI0  
TX9/OEI1  
Connection  
Memory  
Internal  
Registers  
TX15/OEI7  
RX15  
Microprocessor Interface  
Timing Unit  
JTAG Port  
DS  
CS  
DTA  
TRST  
TMS TDI TCK TDO  
C32i F32i FE  
R/W  
A0-A14  
D0-D15  
5933 drw01  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc. TheST-BUS® isatrademarkofMitelCorp.  
JUNE 2004  
1
DSC-5933/10  

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