Datasheet > 72V71660

72V71660

更新时间： 2024-10-02 14:58:23

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
32页	350K
描述
16K x 16K TSI, 64 I/O at 2/4/8 or 16Mbps, 3.3V

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数据手册

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72V71660 数据手册

3.3 VOLT TIME SLOT INTERCHANGE

DIGITAL SWITCH

IDT72V71660

16,384 ^X16,384

FEATURES:

DESCRIPTION:

•

16K x 16K non-blocking switching at 16.384Mb/s

64 serial input and output streams

The IDT72V71660 has a non-blocking switch capacity of 2,048 x 2,048

channels at 2.048Mb/s, 4,096 x 4,096 channels at 4.096Mb/s, and 8,192 x

8,192channelsat8.192Mb/sand16,384x16,384channelsat16.384Mb/s.

With64inputsand64outputs,programmableperstreamcontrol,andavariety

of operating modes the IDT72V71660 is designed for the TDM time slot

interchangefunctionineithervoiceordataapplications.

Accepts data streams at 2.048Mb/s, 4.096Mb/s, 8.192Mb/s or

16.384Mb/s

•

Per-channel Variable Delay Mode for low-latency applications

Per-channel Constant Delay Mode for frame integrity applications

Automatic identification of ST-BUS^®and GCI bus interfaces

Automatic frame offset delay measurement

Per-stream frame delay offset programming

Per-channel high-impedance output control

Direct microprocessor access to all internal memories

Memory block programming for quick setup

IEEE-1149.1 (JTAG) Test Port

Some of the main features of the IDT72V71660 are LOW power 3.3 Volt

operation, automatic ST-BUS^®/GCI sensing, memory block programming,

simplemicroprocessorinterface,onecycledirectinternalmemoryaccesses,

JTAGTestAccessPort(TAP)andperstreamprogrammableinputoffsetdelay,

variableorconstantthroughputmodes,outputenableandprocessormode.

TheIDT72V71660iscapableofswitchingupto16,384x16,384channels

withoutblocking.Designedtoswitch64Kbit/sPCMorNx64Kbit/sdata,the

devicemaintainsframeintegrityindataapplicationsandminimizesthroughput

delay for voice applications on a per-channel basis.

3.3V Power Supply

Available in 208-pin (17mm x 17mm) Plastic Ball Grid Array

(PBGA) and 208-pin (28mm x 28mm) Plastic Quad Flatpack

(PQFP) packages

•

Operating Temperature Range -40°C to +85°C

FUNCTIONAL BLOCK DIAGRAM

RESET

VCC

GND

ODE

TX0

TX1

RX0

RX1

Data Memory

MUX

Receive

Serial Data

Streams

Transmit

Serial Data

Streams

TX3

TX32/OEI0

TX33/OEI1

Connection

Memory

Internal

Registers

TX63/OEI31

RX63

Microprocessor Interface

Timing Unit

JTAG Port

DS CS

DTA

TRST

TMS TDI TCK TDO

CLK FP FE/HCLK WFPS

R/W

A0-A15

D0-D15

5905 drw01

IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc. TheST-BUS^®isatrademarkofMitelCorp.

JUNE 2004

DSC-5905/10

12 3 4 5 6 7...32

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