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72V71623DAG PDF预览

72V71623DAG

更新时间: 2024-11-26 19:54:35
品牌 Logo 应用领域
艾迪悌 - IDT 电信电信集成电路
页数 文件大小 规格书
28页 380K
描述
TQFP-144, Tray

72V71623DAG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TQFP
包装说明:20 X 20 MM, 0.50 MM PITCH, TQFP-144针数:144
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.82
JESD-30 代码:S-PQFP-G144JESD-609代码:e3
长度:20 mm湿度敏感等级:3
功能数量:1端子数量:144
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP144,.87SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.6 mm子类别:Other Telecom ICs
最大压摆率:0.075 mA标称供电电压:3.3 V
表面贴装:YES电信集成电路类型:DIGITAL TIME SWITCH
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:20 mmBase Number Matches:1

72V71623DAG 数据手册

 浏览型号72V71623DAG的Datasheet PDF文件第2页浏览型号72V71623DAG的Datasheet PDF文件第3页浏览型号72V71623DAG的Datasheet PDF文件第4页浏览型号72V71623DAG的Datasheet PDF文件第5页浏览型号72V71623DAG的Datasheet PDF文件第6页浏览型号72V71623DAG的Datasheet PDF文件第7页 
3.3 VOLT TIME SLOT INTERCHANGE  
DIGITAL SWITCH WITH RATE  
MATCHING  
IDT72V71623  
2,048 x 2,048  
Direct microprocessor access to all internal memories  
Memory block programming for quick setup  
IEEE-1149.1 (JTAG) Test Port  
FEATURES:  
Up to 16 serial input and output streams  
Maximum 2,048 x 2,048 channel non-blocking switching  
Accepts data streams at 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s or  
16.384 Mb/s  
Internal Loopback for testing  
Available in 144-pin Thin Quad Flatpack (TQFP) and  
144-pin Ball Grid Array (BGA) packages  
Operating Temperature Range -40°C to +85°C  
3.3V I/O with 5V tolerant inputs and TTL compatible outputs  
Rate matching capability: Mux/Demux mode  
Output Enable Indication pins provided by dedicated pins  
Per-channel Variable Delay mode for low-latency applications  
Per-channel Constant Delay mode for frame integrity applica-  
tions  
DESCRIPTION:  
Automatic identification of ST-BUS® and GCI serial streams  
Automatic frame offset delay measurement  
Per-stream frame delay offset programming  
Per-channel high-impedance output control  
Per-channel Processor mode to allow microprocessor writes to  
TXstreams  
The IDT72V71623 has a maximum non-blocking switch capacity of  
2,048x2,048channelswithdatarates at 2.048Mb/s,4.096Mb/s,8.192Mb/s  
or16.384Mb/s. With16inputsand16outputs,avarietyofratecombinations  
issupportedunderMux/Demuxmode, toallow forswitchingbetweenstreams  
ofdifferentdatarates.  
FUNCTIONAL BLOCK DIAGRAM  
TRST  
RESET  
TMS TDI  
TCK  
ODE  
Vcc GND  
TDO  
Test Port  
TX0  
RX0  
TX1  
Loopback  
TX2  
TX3  
RX1  
TX4  
RX2  
TX5  
TX6  
TX7  
TX8  
TX9  
RX3  
Output  
MUX  
RX4  
TX10  
TX11  
TX12  
TX13  
TX14  
TX15  
OEI0  
OEI1  
OEI2  
OEI3  
OEI4  
OEI5  
OEI6  
OEI7  
OEI8  
OEI9  
OEI10  
OEI11  
OEI12  
OEI13  
OEI14  
OEI15  
Data Memory  
RX5  
RX6  
Transmit  
Serial Data  
Streams  
Receive  
Serial Data  
Streams  
RX7  
RX8  
RX9  
RX10  
RX11  
RX12  
RX13  
RX14  
RX15  
Connection  
Memory  
Internal  
Registers  
Timing Unit  
Microprocessor Interface  
5903 drw01  
CLK F0i FE/ WFPS  
DS  
CS  
A0-A13  
D0-D15  
DTA  
R/W  
HCLK  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc. TheST-BUS® isatrademarkofZarlinkSemiconductor,Inc..  
1
©
2005 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-5903/10  

72V71623DAG 替代型号

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