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72V51246L6BBI PDF预览

72V51246L6BBI

更新时间: 2024-11-28 15:42:03
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
52页 413K
描述
FIFO

72V51246L6BBI 技术参数

是否Rohs认证:不符合生命周期:Obsolete
包装说明:,Reach Compliance Code:not_compliant
风险等级:5.92Is Samacsys:N
JESD-609代码:e0湿度敏感等级:3
端子面层:Tin/Lead (Sn63Pb37)Base Number Matches:1

72V51246L6BBI 数据手册

 浏览型号72V51246L6BBI的Datasheet PDF文件第2页浏览型号72V51246L6BBI的Datasheet PDF文件第3页浏览型号72V51246L6BBI的Datasheet PDF文件第4页浏览型号72V51246L6BBI的Datasheet PDF文件第5页浏览型号72V51246L6BBI的Datasheet PDF文件第6页浏览型号72V51246L6BBI的Datasheet PDF文件第7页 
3.3V MULTI-QUEUE FIFO (4 QUEUES)  
36 BIT WIDE CONFIGURATION  
589,824 bits, 1,179,648 bits and  
2,359,296 bits  
PRELIMINARY  
IDT72V51236  
IDT72V51246  
IDT72V51256  
4 bit parallel flag status on both read and write ports  
FEATURES:  
Provides continuous PAE and PAF status of up to 4 Queues  
Global Bus Matching - (All Queues have same Input Bus Width  
and Output Bus Width)  
User Selectable Bus Matching Options:  
- x36in to x36out  
- x18in to x36out  
- x9in to x36out  
- x36in to x18out  
- x36in to x9out  
Choose from among the following memory density options:  
IDT72V51236  
IDT72V51246  
IDT72V51256  
Total Available Memory = 589,824 bits  
Total Available Memory = 1,179,648 bits  
Total Available Memory = 2,359,296 bits  
Configurable from 1 to 4 Queues  
Queues may be configured at master reset from the pool of  
Total Available Memory in blocks of 256 x 36  
Independent Read and Write access per queue  
User programmable via serial port  
Default Multi-Queue device configurations  
-IDT72V51236: 4,096 x 36 x 4Q  
FWFT mode of operation on read port  
Packet Ready mode of operation  
Partial Reset, clears data in single Queue  
Expansion of up to 8 Multi-Queue devices in parallel is available  
JTAG Functionality (Boundary Scan)  
Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm  
HIGH Performance submicron CMOS technology  
Industrial temperature range (-40°C to +85°C) is available  
-IDT72V51246: 8,192 x 36 x 4Q  
-IDT72V51256: 16,384 x 36 x 4Q  
100% Bus Utilization, Read and Write on every clock cycle  
166 MHz High speed operation (6ns cycle time)  
3.7ns access time  
Individual, Active queue flags (OV, FF, PAE, PAF, PR)  
DATA PATH FLOW DIAGRAM  
MULTI-QUEUE FIFO  
WADEN  
FSTR  
RADEN  
ESTR  
Q
0
RDADD  
6
WRADD  
5
REN  
WEN  
RCLK  
WCLK  
OE  
Q
D
in  
out  
x9, x18, x36  
DATA OUT  
x9, x18, x36  
DATA IN  
OV  
FF  
Q
3
PR  
PAF  
PAE  
PAFn  
4
PAEn/PRn  
4
5937 drw01  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc  
JANUARY 2002  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
1
2002 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-5937/4  

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