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72V3682L15PF8 PDF预览

72V3682L15PF8

更新时间: 2024-11-26 05:32:27
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
29页 252K
描述
TQFP-120, Reel

72V3682L15PF8 数据手册

 浏览型号72V3682L15PF8的Datasheet PDF文件第2页浏览型号72V3682L15PF8的Datasheet PDF文件第3页浏览型号72V3682L15PF8的Datasheet PDF文件第4页浏览型号72V3682L15PF8的Datasheet PDF文件第5页浏览型号72V3682L15PF8的Datasheet PDF文件第6页浏览型号72V3682L15PF8的Datasheet PDF文件第7页 
3.3 VOLT CMOS SyncBiFIFOTM  
16,384 x 36 x 2  
32,768 x 36 x 2  
IDT72V3682  
IDT72V3692  
IDT72V36102  
65,536 x 36 x 2  
Mailbox bypass register for each FIFO  
Programmable Almost-Full and Almost-Empty flags  
Microprocessor Interface Control Logic  
FEATURES  
Memory storage capacity:  
IDT72V3682 – 16,384 x 36 x 2  
FFA/IRA, EFA/ORA, AEA, and AFA flags synchronized by CLKA  
FFB/IRB, EFB/ORB, AEB, and AFB flags synchronized by CLKB  
Select IDT Standard timing (using EFA, EFB, FFA and FFB flags  
functions) or First Word Fall Through timing (using ORA, ORB, IRA  
and IRB flag functions)  
Available in space-saving 120-pin Thin Quad Flatpack (TQFP)  
Pin compatible to the lower density parts, IDT72V3622/72V3632/  
72V3642/72V3652/72V3662/72V3672  
IDT72V3692 – 32,768 x 36 x 2  
IDT72V36102 – 65,536 x 36 x 2  
Supports clock frequencies up to 100MHz  
Fast access times of 6.5ns  
Free-running CLKA and CLKB may be asynchronous or coincident  
(simultaneous reading and writing of data on a single clock edge  
is permitted)  
Two independent clocked FIFOs buffering data in opposite direc-  
tions  
Industrial temperature range (–40°C to +85°C) is available  
Green parts available, see ordering information  
FUNCTIONAL BLOCK DIAGRAM  
MBF1  
Mail 1  
Register  
CLKA  
CSA  
Port-A  
Control  
Logic  
W/RA  
RAM  
ARRAY  
16,384 x 36  
32,768 x 36  
65,536 x 36  
ENA  
MBA  
36  
FIFO1,  
Mail1  
Reset  
Logic  
RST1  
Write  
Pointer  
Read  
Pointer  
36  
Status Flag  
Logic  
EFB/ORB  
AEB  
FFA/IRA  
AFA  
FIFO 1  
FS  
0
1
Programmable Flag  
Offset Registers  
Timing  
Mode  
FWFT  
FS  
A
0
- A35  
16  
B0 - B35  
FIFO 2  
Status Flag  
EFA/ORA  
FFB/IRB  
AFB  
Logic  
AEA  
36  
Read  
Pointer  
Write  
Pointer  
36  
FIFO2,  
Mail2  
Reset  
Logic  
RST2  
RAM  
ARRAY  
16,384 x 36  
32,768 x 36  
65,536 x 36  
CLKB  
CSB  
Port-B  
Control  
Logic  
W/RB  
ENB  
Mail 2  
Register  
MBB  
4679 drw 01  
MBF2  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc. TheSyncBiFIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL TEMPERATURE RANGE  
FEBRUARY 2009  
1
©
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-4679/6  

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