3.3VOLTCMOSCLOCKEDFIFOWITH
BUS-MATCHINGANDBYTESWAPPING
64 x 36
IDT72V3613
• Parity Generation can be selected for each Port
FEATURES:
• Available in 132-pin plastic quad flat package (PQF), or space
saving 120-pin thin quad flat package (TQFP)
• Pin and functionally compatible version of the 5V operating
IDT723613
• Industrial temperature range (–40°C to +85°C) is available
• Green parts available, see ordering information
• 64 x 36 storage capacity FIFO buffering data from Port A to Port B
• Supports clock frequencies up to 83MHz
• Fast access times of 8ns
• Free-running CLKA and CLKB may be asynchronous or
coincident (permits simultaneous reading and writing of data on
a single clock edge)
• Mailbox bypass registers in each direction
• Dynamic Port B bus sizing of 36 bits (long word), 18 bits (word),
and 9 bits (byte)
• Selection of Big- or Little-Endian format for word and byte bus
sizes
• Three modes of byte-order swapping on Port B
• Programmable Almost-Full and Almost-Empty flags
• Microprocessor interface control logic
• FF , AF flags synchronized by CLKA
• EF , AE flags synchronized by CLKB
• Passive parity checking on each Port
DESCRIPTION:
The IDT72V3613 is a pin and functionally compatible version of the
IDT723613, designed to run off a 3.3V supply for exceptionally low-power
consumption. This device is a monolithic, high-speed, low-power, CMOS
synchronous(clocked)FIFOmemorywhichsupportsclockfrequenciesupto
83MHzandhasread-accesstimesasfastas8ns.The64x36dual-portSRAM
FIFO buffers data from port A to port B. The FIFO operates in IDT Standard
modeandhasflagstoindicateemptyandfullconditions,andtwoprogrammable
flags, Almost-Full(AF)andAlmost-Empty(AE), toindicate whena selected
numberofwordsisstoredinmemory.FIFOdataonportBcanbeoutputin36-
FUNCTIONALBLOCKDIAGRAM
CLKA
CSA
W/RA
ENA
Port-A
Control
Logic
MBA
MBF1
PEFB
Parity
Gen/Check
Mail 1
Register
RST
PGB
Device
Control
ODD/
EVEN
RAM ARRAY
64 x 36
64 x 36
36
36
Read
Pointer
Write
Pointer
B0 - B35
Status Flag
FF
AF
EF
Logic
AE
FIFO
CLKB
CSB
W/RB
ENB
BE
SIZ0
SIZ1
SW0
SW1
Programmable
Flag Offset
Registers
FS
0
1
Port-B
Port-B
FS
Control
Control
Logic
A - A35
0
Logic
PGA
Mail 2
Register
Parity
Gen/Check
PEFA
MBF2
4661 drw 01
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.SyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL TEMPERATURE RANGE
FEBRUARY 2009
1
©2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4661/3