Datasheet > 72V36100

72V36100

更新时间： 2024-11-06 14:56:07

品牌	Logo	应用领域
瑞萨 - RENESAS		先进先出芯片
页数	文件大小	规格书
49页	709K
描述
64K x 36 SuperSync II FIFO, 3.3V

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中文翻译

获取价格

数据手册

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72V36100 数据手册

3.3 VOLT HIGH-DENSITY SUPERSYNC II™ 36-BIT FIFO

65,536 x 36

131,072 x 36

72V36100

72V36110

• Empty, Full and Half-Full flags signal FIFO status

• Programmable Almost-Empty and Almost-Full flags, each flag can

default to one of eight preselected offsets

• Selectable synchronous/asynchronous timing modes for Almost-

Empty and Almost-Full flags

• Program programmable flags by either serial or parallel means

• Select Standard timing (using EF and FF flags) or First Word Fall

Through timing (using OR and IR flags)

• Output enable puts data outputs into high impedance state

• Easily expandable in depth and width

• JTAG port, provided for Boundary Scan function (PBGA & CABGA

Only)

• Independent Read and Write Clocks (permit reading and writing

simultaneously)

• Availableina128-pinThinQuadFlatPack(TQFP)ora144-pinPlastic

Ball Grid Array (PBGA) (with additional features), or a 144-pin Chip

Array BGA (CABGA) (with additional features)

FEATURES:

• Choose among the following memory organizations:

72V36100

72V36110

⎯

65,536 x 36

131,072 x 36

• Higher density, 2Meg and 4Meg SuperSync II FIFOs

• Up to 166 MHz Operation of the Clocks

• UserselectableAsynchronousreadand/orwriteports(PBGA&CABGA

Only)

• User selectable input and output port bus-sizing

- x36 in to x36 out

- x36 in to x18 out

- x36 in to x9 out

- x18 in to x36 out

- x9 in to x36 out

• Big-Endian/Little-Endian user selectable byte representation

• 5V input tolerant

• Fixed, low first word latency

• Pin compatible to the SuperSync II (72V3640/72V3650/72V3660/

72V3670/72V3680/72V3690)family

• High-performance submicron CMOS technology

• Industrial temperature range (–40°C to +85°C) is available

• Green parts available, see ordering information

• Zero latency retransmit

• Auto power down minimizes standby power consumption

• Master Reset clears entire FIFO

• Partial Reset clears data, but retains programmable settings

FUNCTIONALBLOCKDIAGRAM

*Available on the PBGA & CABGA packages only.

D0 -Dn (x36, x18 or x9)

LD SEN

WEN

WCLK/WR

INPUT REGISTER

OFFSET REGISTER

FF/IR

PAF

EF/OR

FLAG

LOGIC

PAE

FWFT/SI

PFM

FSEL0

FSEL1

WRITE CONTROL

LOGIC

ASYW

RAM ARRAY

65,536 x 36

131,072 x 36

WRITE POINTER

READ POINTER

CONTROL

LOGIC

ASYR

READ

CONTROL

LOGIC

OUTPUT REGISTER

BUS

CONFIGURATION

MRS

PRS

RESET

LOGIC

RCLK/RD

REN

TCK

TRST

TMS

TDI

TDO

JTAG CONTROL

(BOUNDARY

SCAN)

6117 drw01

Q0 -Qn (x36, x18 or x9)

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

May.25.23

12 3 4 5 6 7...49

中文翻译

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与72V36100相关器件

型号	品牌	获取价格	描述	数据表
72V36100L10BBG	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II
72V36100L10BBG8	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II
72V36100L10BBGI	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II
72V36100L10BBGI8	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II
72V36100L10PF8	IDT	获取价格	TQFP-128, Reel
72V36100L10PF9	IDT	获取价格	FIFO, 64KX36, 6.5ns, Synchronous, CMOS, PQFP128, PLASTIC, TQFP-128
72V36100L10PFG	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II
72V36100L10PFG8	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II
72V36100L10PFGI	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II
72V36100L10PFGI8	IDT	获取价格	3.3 VOLT HIGH-DENSITY SUPERSYNC II

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