Datasheet > 72V255LA20PF

72V255LA20PF

更新时间： 2024-12-02 10:39:03

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
27页	244K
描述
TQFP-64, Tray

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中文翻译

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数据手册

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72V255LA20PF 数据手册

3.3 VOLT CMOS SuperSync FIFO™

8,192 x 18

16,384 x 18

IDT72V255LA

IDT72V265LA

• Output enable puts data outputs into high impedance state

• Easily expandable in depth and width

• Independent Read and Write clocks (permit reading and

writing simultaneously)

• Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-

pin Slim Thin Quad Flat Pack (STQFP)

• High-performance submicron CMOS technology

• Industrial temperature range (–40°C to +85°C) is available

• Green parts available, see ordering information

FEATURES:

• Choose among the following memory organizations:

IDT72V255LA

IDT72V265LA

8,192 x 18

16,384 x 18

• Pin-compatible with the IDT72V275/72V285 and IDT72V295/

72V2105 SuperSync FIFOs

• Functionally compatible with the 5 Volt IDT72255/72265 family

• 10ns read/write cycle time (6.5ns access time)

• Fixed, low first word data latency time

• 5V input tolerant

DESCRIPTION:

• Auto power down minimizes standby power consumption

• Master Reset clears entire FIFO

• Partial Reset clears data, but retains programmable settings

• Retransmit operation with fixed, low first word data

latency time

• Empty, Full and Half-Full flags signal FIFO status

• Programmable Almost-Empty and Almost-Full flags, each flag

can default to one of two preselected offsets

• Program partial flags by either serial or parallel means

• Select IDT Standard timing (using EF and FF flags) or First

Word Fall Through timing (using OR and IR flags)

TheIDT72V255LA/72V265LAarefunctionallycompatibleversionsofthe

IDT72255/72265 designed to run off a 3.3V supply for very low power

consumption. TheIDT72V255LA/72V265LAareexceptionallydeep,high

speed, CMOS First-In-First-Out (FIFO) memories with clocked read and

writecontrols. TheseFIFOs offernumerous improvements overprevious

SuperSyncFIFOs,includingthefollowing:

• Thelimitationofthefrequencyofoneclockinputwithrespecttotheother

has beenremoved. TheFrequencySelectpin(FS)has beenremoved,

thusitisnolongernecessarytoselectwhichofthetwoclockinputs,RCLK

or WCLK, is running at the higher frequency.

FUNCTIONAL BLOCK DIAGRAM

D0 -D17

WEN

WCLK

SEN

OFFSET REGISTER

INPUT REGISTER

FF/IR

PAF

EF/OR

PAE

FLAG

LOGIC

WRITE CONTROL

LOGIC

FWFT/SI

RAM ARRAY

8,192 x 18

16,384 x 18

WRITE POINTER

READ POINTER

READ

CONTROL

LOGIC

OUTPUT REGISTER

MRS

PRS

RESET

LOGIC

RCLK

REN

4672 drw 01

Q0 -Q17

IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,IncandtheSuperSyncFIFOisatrademark ofIntegratedDeviceTechnology,Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

OCTOBER 2008

DSC-4672/3

12 3 4 5 6 7...27

中文翻译

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与72V255LA20PF相关器件

型号	品牌	获取价格	描述	数据表
72V255LA20PF9	IDT	获取价格	FIFO, 8KX18, 12ns, Synchronous, CMOS, PQFP64, TQFP-64
72V255LA20PFG	IDT	获取价格	FIFO, 8KX18, 12ns, Synchronous, CMOS, PQFP64, GREEN, PLASTIC, TQFP-64
72V255LA20PFG8	IDT	获取价格	3.3 VOLT CMOS SuperSync FIFO
72V255LA20PFGI	IDT	获取价格	3.3 VOLT CMOS SuperSync FIFO
72V255LA20PFGI8	IDT	获取价格	3.3 VOLT CMOS SuperSync FIFO
72V255LA20TF	IDT	获取价格	TQFP-64, Tray
72V255LA20TF9	IDT	获取价格	FIFO, 8KX18, 12ns, Synchronous, CMOS, PQFP64, STQFP-64
72V255LA20TFG	IDT	获取价格	FIFO, 8KX18, 12ns, Synchronous, CMOS, PQFP64, GREEN, SLIM, TQFP-64
72V255LA20TFG8	IDT	获取价格	3.3 VOLT CMOS SuperSync FIFO
72V255LA20TFGI	IDT	获取价格	3.3 VOLT CMOS SuperSync FIFO

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