3.3 VOLT CMOS SyncFIFO™
256 x 9, 512 x 9,
1,024 x 9, 2,048 x 9,
IDT72V201, IDT72V211
IDT72V221, IDT72V231
IDT72V241, IDT72V251
4,096 x 9 and 8,192 x 9
are very high-speed, low-power First-In, First-Out (FIFO) memories with
clockedreadandwritecontrols.Thearchitecture,functionaloperationandpin
assignments are identical to those of the IDT72201/72211/72221/72231/
72241/72251,butoperateatapowersupplyvoltage(Vcc)between3.0Vand
3.6V. These devices have a 256, 512, 1,024, 2,048, 4,096 and 8,192 x 9-
bitmemoryarray,respectively.TheseFIFOsareapplicableforawidevariety
ofdatabufferingneedssuchasgraphics,localareanetworksandinterprocessor
communication.
FEATURES:
• 256 x 9-bit organization IDT72V201
• 512 x 9-bit organization IDT72V211
• 1,024 x 9-bit organization IDT72V221
• 2,048 x 9-bit organization IDT72V231
• 4,096 x 9-bit organization IDT72V241
• 8,192 x 9-bit organization IDT72V251
• 10 ns read/write cycle time
These FIFOs have 9-bit input and output ports. The input port is
controlled by a free-running clock (WCLK), and two Write Enable pins
(WEN1, WEN2). Data is written into the Synchronous FIFO on every
rising clock edge when the Write Enable pins are asserted. The output
port is controlled by another clock pin (RCLK) and two Read Enable pins
(REN1, REN2). The Read Clock can be tied to the Write Clock for single
clock operation or the two clocks can run asynchronous of one another
for dual-clock operation. An Output Enable pin (OE) is provided on the
read port for three-state control of the output.
TheSynchronousFIFOshavetwofixedflags,Empty(EF)andFull(FF).
Twoprogrammableflags,Almost-Empty(PAE)andAlmost-Full(PAF),are
provided for improved system control. The programmable flags default to
Empty+7andFull-7forPAEandPAF,respectively.Theprogrammableflag
offsetloadingiscontrolledbyasimplestatemachineandisinitiatedbyasserting
the Load pin (LD).
• 5V input tolerant
• Read and Write clocks can be independent
• Dual-Ported zero fall-through time architecture
• Empty and Full Flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags can be set to
any depth
• Programmable Almost-Empty and Almost-Full flags default to
Empty+7, and Full-7, respectively
• Output Enable puts output data bus in high-impedance state
• Advanced submicron CMOS technology
• Available in 32-pin plastic leaded chip carrier (PLCC) and 32-pin
plastic Thin Quad FlatPack (TQFP)
• Industrial temperature range (–40°C to +85°C) is available
• Green parts available, see ordering information
These FIFOs are fabricated using high-speed submicron CMOS
technology.
DESCRIPTION:
TheIDT72V201/72V211/72V221/72V231/72V241/72V251SyncFIFOs™
FUNCTIONAL BLOCK DIAGRAM
D0 - D8
WCLK
WEN1
WEN2
LD
INPUT REGISTER
OFFSET REGISTER
EF
FLAG
LOGIC
PAE
PAF
FF
WRITE CONTROL
LOGIC
RAM ARRAY
256 x 9, 512 x 9,
1,024 x 9, 2,048 x 9,
4,096 x 9, 8,192 x 9
READ POINTER
WRITE POINTER
READ CONTROL
LOGIC
OUTPUT REGISTER
RESET LOGIC
RCLK
REN1
REN2
RS
OE
4092 drw 01
Q0 - Q8
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.SyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
AUGUST 2013
1
©2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4092/6