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72V215L15PFI PDF预览

72V215L15PFI

更新时间: 2024-11-27 09:04:03
品牌 Logo 应用领域
艾迪悌 - IDT 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
25页 401K
描述
TQFP-64, Tray

72V215L15PFI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TQFP
包装说明:PLASTIC, TQFP-64针数:64
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.79
最长访问时间:10 ns最大时钟频率 (fCLK):66.7 MHz
周期时间:15 nsJESD-30 代码:S-PQFP-G64
JESD-609代码:e0长度:14 mm
内存密度:9216 bit内存集成电路类型:OTHER FIFO
内存宽度:18湿度敏感等级:3
功能数量:1端子数量:64
字数:512 words字数代码:512
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:512X18
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP64,.66SQ,32
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):240
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.6 mm最大待机电流:0.005 A
子类别:FIFOs最大压摆率:0.03 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:14 mm
Base Number Matches:1

72V215L15PFI 数据手册

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3.3 VOLT CMOS SyncFIFOTM  
256 x 18, 512 x 18, 1,024 x 18,  
2,048 x 18, and 4,096 x 18  
IDT72V205, IDT72V215,  
IDT72V225, IDT72V235,  
IDT72V245  
Industrial temperature range (–40°C to +85°C) is available  
Green parts available, see ordering information  
FEATURES:  
256 x 18-bit organization array (IDT72V205)  
512 x 18-bit organization array (IDT72V215)  
1,024 x 18-bit organization array (IDT72V225)  
2,048 x 18-bit organization array (IDT72V235)  
4,096 x 18-bit organization array (IDT72V245)  
10 ns read/write cycle time  
DESCRIPTION:  
TheIDT72V205/72V215/72V225/72V235/72V245arefunctionallycom-  
patibleversionsoftheIDT72205LB/72215LB/72225LB/72235LB/72245LB,  
designed to run off a 3.3V supply for exceptionally low power consumption.  
These devices are very high-speed, low-power First-In, First-Out (FIFO)  
memorieswithclockedreadandwritecontrols. TheseFIFOsareapplicable  
forawidevarietyofdatabufferingneeds,suchasopticaldiskcontrollers,Local  
AreaNetworks(LANs),andinterprocessorcommunication.  
5V input tolerant  
IDT Standard or First Word Fall Through timing  
Single or double register-buffered Empty and Full flags  
Easily expandable in depth and width  
Asynchronous or coincident Read and Write Clocks  
Asynchronous or synchronous programmable Almost-Empty  
and Almost-Full flags with default settings  
Half-Full flag capability  
Output enable puts output data bus in high-impedance state  
High-performance submicron CMOS technology  
Available in a 64-lead thin quad flatpack (TQFP/STQFP)  
TheseFIFOshave18-bitinputandoutputports. Theinputportiscontrolled  
byafree-runningclock(WCLK),andaninputenablepin(WEN).Dataisread  
intothesynchronousFIFOoneveryclockwhenWENisasserted.Theoutput  
portiscontrolledbyanotherclockpin(RCLK)andanotherenablepin(REN).  
TheReadClock(RCLK)canbetiedtotheWriteClockforsingleclockoperation  
orthetwoclockscanrunasynchronousofoneanotherfordual-clockoperation.  
AnOutputEnablepin(OE)isprovidedonthereadportforthree-statecontrol  
oftheoutput.  
FUNCTIONAL BLOCK DIAGRAM  
WCLK  
D0-D17  
LD  
WEN  
INPUT REGISTER  
OFFSET REGISTER  
FF/IR  
PAF  
FLAG  
WRITE CONTROL  
LOGIC  
EF/OR  
PAE  
LOGIC  
RAM ARRAY  
256 x 18, 512 x 18  
1,024 x 18, 2,048 x 18  
4,096 x 18  
HF/(WXO)  
READ POINTER  
WRITE POINTER  
FL  
WXI  
READ CONTROL  
LOGIC  
EXPANSION LOGIC  
(HF)/WXO  
RXI  
RXO  
OUTPUT REGISTER  
RESET LOGIC  
RS  
4294 drw 01  
OE  
REN  
RCLK  
Q0-Q17  
IDT, IDTlogoareregisteredtrademarksofIntegratedDeviceTechnology, Inc. SyncFIFOisatrademarkofIntegratedDeviceTechnology, Inc.  
MARCH 2013  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
1
©2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-4294/7  

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