Datasheet > 72V205L15TFI9

72V205L15TFI9

更新时间： 2024-09-16 06:25:15

品牌	Logo	应用领域
艾迪悌 - IDT		先进先出芯片
页数	文件大小	规格书
25页	286K
描述
FIFO, 256X18, 10ns, Synchronous, CMOS, PQFP64, PLASTIC, STQFP-64

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72V205L15TFI9 数据手册

3.3 VOLT CMOS SyncFIFO^TM

256 x 18, 512 x 18, 1,024 x 18,

2,048 x 18, and 4,096 x 18

IDT72V205, IDT72V215,

IDT72V225, IDT72V235,

IDT72V245

FEATURES:

DESCRIPTION:

• 256 x 18-bit organization array (IDT72V205)

• 512 x 18-bit organization array (IDT72V215)

• 1,024 x 18-bit organization array (IDT72V225)

• 2,048 x 18-bit organization array (IDT72V235)

• 4,096 x 18-bit organization array (IDT72V245)

• 10 ns read/write cycle time

TheIDT72V205/72V215/72V225/72V235/72V245arefunctionallycom-

patibleversionsoftheIDT72205LB/72215LB/72225LB/72235LB/72245LB,

designed to run off a 3.3V supply for exceptionally low power consumption.

These devices are very high-speed, low-power First-In, First-Out (FIFO)

memorieswithclockedreadandwritecontrols. TheseFIFOsareapplicable

forawidevarietyofdatabufferingneeds,suchasopticaldiskcontrollers,Local

AreaNetworks(LANs),andinterprocessorcommunication.

• 5V input tolerant

• IDT Standard or First Word Fall Through timing

• Single or double register-buffered Empty and Full flags

• Easily expandable in depth and width

• Asynchronous or coincident Read and Write Clocks

• Asynchronous or synchronous programmable Almost-Empty

and Almost-Full flags with default settings

• Half-Full flag capability

• Output enable puts output data bus in high-impedanc state

• High-performance submicron CMOS technology

• Available in a 64-lead thin quad flatpack (TQFP/STQFP)

• Industrial temperature range (–40°C to +85°C) is available

TheseFIFOshave18-bitinputandoutputports. Theinputportiscontrolled

byafree-runningclock(WCLK),andaninputenablepin(WEN).Dataisread

intothesynchronousFIFOoneveryclockwhenWENisasserted.Theoutput

portiscontrolledbyanotherclockpin(RCLK)andanotherenablepin(REN).

TheReadClock(RCLK)canbetiedtotheWriteClockforsingleclockoperation

orthetwoclockscanrunasynchronousofoneanotherfordual-clockoperation.

AnOutputEnablepin(OE)isprovidedonthereadportforthree-statecontrol

oftheoutput.

ThesynchronousFIFOshavetwofixedflags,EmptyFlag/OutputReady

(EF/OR) and Full Flag/Input Ready (FF/IR), and two programmable flags,

Almost-Empty(PAE)andAlmost-Full(PAF). Theoffsetloadingoftheprogram-

FUNCTIONAL BLOCK DIAGRAM

WCLK

D0-D17

WEN

INPUT REGISTER

OFFSET REGISTER

FF/IR

PAF

FLAG

WRITE CONTROL

LOGIC

EF/OR

PAE

LOGIC

RAM ARRAY

256 x 18, 512 x 18

1,024 x 18, 2,048 x 18

4,096 x 18

HF/(WXO)

READ POINTER

WRITE POINTER

WXI

READ CONTROL

LOGIC

EXPANSION LOGIC

(HF)/WXO

RXI

RXO

OUTPUT REGISTER

RESET LOGIC

4294 drw 01

REN

RCLK

Q0-Q17

IDTandtheIDTlogoaretrademarksofIntegratedDeviceTechnology, Inc. SyncFIFOisatrademarkofIntegratedDeviceTechnology, Inc.

FEBRUARY 2002

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

DSC-4294/4

12 3 4 5 6 7...25

中文翻译

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与72V205L15TFI9相关器件

型号	品牌	获取价格	描述	数据表
72V205L20PFG	IDT	获取价格	FIFO, 256X18, 12ns, Synchronous, CMOS, PQFP64, GREEN, PLASTIC, TQFP-64
72V205L20PFG8	IDT	获取价格	FIFO, 256X18, 12ns, Synchronous, CMOS, PQFP64, GREEN, PLASTIC, TQFP-64
72V205L20PFGI	IDT	获取价格	3.3 VOLT CMOS SyncFIFO
72V205L20PFGI8	IDT	获取价格	3.3 VOLT CMOS SyncFIFO
72V205L20TF	IDT	获取价格	TQFP-64, Tray
72V205L20TFG	IDT	获取价格	3.3 VOLT CMOS SyncFIFO
72V205L20TFG8	IDT	获取价格	3.3 VOLT CMOS SyncFIFO
72V205L20TFGI	IDT	获取价格	3.3 VOLT CMOS SyncFIFO
72V205L20TFGI8	IDT	获取价格	3.3 VOLT CMOS SyncFIFO
72V2101	RENESAS	获取价格	256K x 9 SuperSync FIFO, 3.3V

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