Datasheet > 72271

72271

更新时间： 2023-12-20 18:44:33

品牌	Logo	应用领域
瑞萨 - RENESAS		先进先出芯片
页数	文件大小	规格书
28页	531K
描述
32K x 9 SuperSync FIFO, 5.0V

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数据手册

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72271 数据手册

CMOS SuperSync FIFO^™

16,384 x 9

32,768 x 9

IDT72261LA

IDT72271LA

LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

• Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-

pin Slim Thin Quad Flat Pack (STQFP)

• High-performance submicron CMOS technology

• Industrial temperature range (–40°C to +85°C) is available

• Green parts available, see ordering information

FEATURES:

• Choose among the following memory organizations:

IDT72261LA 16,384 x 9

IDT72271LA 32,768 x 9

• Pin-compatible with the IDT72281/72291 SuperSync FIFOs

• 10ns read/write cycle time (8ns access time)

• Fixed, low first word data latency time

• Auto power down minimizes standby power consumption

• Master Reset clears entire FIFO

• Partial Reset clears data, but retains programmable settings

• Retransmit operation with fixed, low first word data latency time

• Empty, Full and Half-Full flags signal FIFO status

• Programmable Almost-Empty and Almost-Full flags, each flag

can default to one of two preselected offsets

• Program partial flags by either serial or parallel means

• Select IDT Standard timing (using EF and FF flags) or First

Word Fall Through timing (using OR and IR flags)

• Output enable puts data outputs into high impedance state

• Easily expandable in depth and width

DESCRIPTION:

The IDT72261LA/72271LA are exceptionally deep, high speed, CMOS

First-In-First-Out (FIFO) memories with clocked read and write controls.

These FIFOs offer numerous improvements over previous SuperSync

FIFOs, including the following:

• Thelimitationofthefrequencyofoneclockinputwithrespecttotheother

has been removed. The Frequency Select pin (FS) has been removed,

thus it is no longer necessary to select which of the two clock inputs,

RCLK or WCLK, is running at the higher frequency.

• The period required by the retransmit operation is now fixed and short.

• The first word data latency period, from the time the first word is written

to an empty FIFO to the time it can be read, is now fixed and short. (The

variableclockcyclecountingdelayassociatedwiththelatencyperiodfound

on previous SuperSync devices has been eliminated on this SuperSync

family.)

• Independent Read and Write clocks (permit reading and writing

simultaneously)

FUNCTIONAL BLOCK DIAGRAM

D0 -D8

WEN

WCLK

SEN

OFFSET REGISTER

INPUT REGISTER

FF/IR

PAF

EF/OR

PAE

FLAG

LOGIC

WRITE CONTROL

LOGIC

FWFT/SI

RAM ARRAY

16,384 x 9

32,768 x 9

WRITE POINTER

READ POINTER

READ

CONTROL

LOGIC

OUTPUT REGISTER

MRS

PRS

RESET

LOGIC

RCLK

REN

Q0 -Q8

4671 drw 01

IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.TheSuperSyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.

FEBRUARY 2018

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

DSC-4671/6

12 3 4 5 6 7...28

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