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7204L35TPGI8 PDF预览

7204L35TPGI8

更新时间: 2024-11-13 00:32:35
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
14页 143K
描述
CMOS ASYNCHRONOUS FIFO

7204L35TPGI8 数据手册

 浏览型号7204L35TPGI8的Datasheet PDF文件第2页浏览型号7204L35TPGI8的Datasheet PDF文件第3页浏览型号7204L35TPGI8的Datasheet PDF文件第4页浏览型号7204L35TPGI8的Datasheet PDF文件第5页浏览型号7204L35TPGI8的Datasheet PDF文件第6页浏览型号7204L35TPGI8的Datasheet PDF文件第7页 
IDT7203  
IDT7204  
IDT7205  
IDT7206  
IDT7207  
IDT7208  
CMOS ASYNCHRONOUS FIFO  
2,048 x 9, 4,096 x 9  
8,192 x 9, 16,384 x 9  
32,768 x 9 and 65,536 x 9  
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018  
Industrial temperature range (–40  
(plastic packages only)  
°C to +85°C) is available  
FEATURES:  
First-In/First-Out Dual-Port memory  
Green parts available, see ordering information  
2,048 x 9 organization (IDT7203)  
4,096 x 9 organization (IDT7204)  
DESCRIPTION:  
8,192 x 9 organization (IDT7205)  
16,384 x 9 organization (IDT7206)  
32,768 x 9 organization (IDT7207)  
65,636 x 9 organization (IDT7208)  
High-speed: 12ns access time  
Low power consumption  
TheIDT7203/7204/7205/7206/7207/7208aredual-portmemorybuffers  
withinternalpointersthatloadandemptydataonafirst-in/first-outbasis. The  
deviceusesFullandEmptyflagstopreventdataoverflowandunderflowand  
expansionlogictoallowforunlimitedexpansioncapabilityinbothwordsizeand  
depth.  
— Active: 660mW (max.)  
— Power-down: 44mW (max.)  
DataistoggledinandoutofthedevicethroughtheuseoftheWrite(W)and  
Read (R) pins.  
Asynchronous and simultaneous read and write  
Fully expandable in both word depth and width  
720x family is pin and functionally compatible from 256 x 9 to 64k x 9  
Status Flags: Empty, Half-Full, Full  
Retransmit capability  
High-performance CMOS technology  
Military product compliant to MIL-STD-883, Class B  
Standard Military Drawing for #5962-88669 (IDT7203), 5962-89567  
(IDT7203), and 5962-89568 (IDT7204) are listed on this function  
The device's 9-bit width provides a bit for a control or parity at the user’s  
option. ItalsofeaturesaRetransmit(RT)capabilitythatallowsthereadpointer  
to be reset to its initial position when RT is pulsed LOW. A Half-Full Flag is  
available in the single device and width expansion modes.  
These FIFOs are fabricated using high-speed CMOS technology. They  
aredesignedforapplicationsrequiringasynchronousandsimultaneousread/  
writesinmultiprocessing,ratebufferingandotherapplications.  
MilitarygradeproductismanufacturedincompliancewithMIL-STD-883,  
ClassB.  
FUNCTIONAL BLOCK DIAGRAM  
DATA INPUTS  
)
8
0
(D -D  
WRITE  
CONTROL  
W
RAM ARRAY  
2,048 x 9  
4,096 x 9  
8,192 x 9  
16,384 x 9  
32,768 x 9  
65,536 x 9  
WRITE  
POINTER  
READ  
POINTER  
THREE-  
STATE  
BUFFERS  
RS  
DATA OUTPUTS  
)
READ  
CONTROL  
8
(Q0-Q  
RESET  
LOGIC  
R
FLAG  
LOGIC  
EF  
FF  
FL/RT  
EXPANSION  
LOGIC  
XO/HF  
XI  
2661 drw01  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.  
COMMERCIAL, MILITARY AND INDUSTRIAL TEMPERATURE RANGES  
1
© 2017 Integrated Device Technology, Inc. All rights reserved. Product subject to change without notice.  
NOVEMBER 2017  
DSC-2661/19  

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