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71V6790375PFGI8 PDF预览

71V6790375PFGI8

更新时间： 2024-01-13 19:32:00
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
20页 248K
描述
3.3V Synchronous SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs, Single Cycle Deselect

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71V6790375PFGI8 技术参数

生命周期：Active包装说明：QFP,
Reach Compliance Code：compliantHTS代码：8542.32.00.41
风险等级：5.64最长访问时间：7.5 ns
其他特性：FLOW THROUGH ARCHITECTUREJESD-30 代码：R-PQFP-G100
内存密度：9437184 bit内存集成电路类型：CACHE SRAM
内存宽度：18功能数量：1
端子数量：100字数：524288 words
字数代码：512000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：512KX18封装主体材料：PLASTIC/EPOXY
封装代码：QFP封装形状：RECTANGULAR
封装形式：FLATPACK并行/串行：PARALLEL
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子位置：QUAD

71V6790375PFGI8 数据手册

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256K X 36, 512K X 18  
3.3VSynchronousSRAMs  
IDT71V67703  
IDT71V67903  
3.3V I/O, Burst Counter  
Flow-ThroughOutputs,SingleCycleDeselect  
Features  
256K x 36, 512K x 18 memory configurations  
Supports fast access times:  
◆
3.3V core power supply  
Power down controlled by ZZ input  
3.3V I/O supply (VDDQ)  
Packaged in a JEDEC Standard 100-pin thin plastic quad  
flatpack(TQFP),119ballgridarray(BGA)and165finepitchball  
grid array (fBGA)  
– 7.5ns up to 117MHz clock frequency  
– 8.0ns up to 100MHz clock frequency  
– 8.5ns up to 87MHz clock frequency  
◆
LBO input selects interleaved or linear burst mode  
Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite  
enable (BWE), and byte writes (BWx)  
Green parts available see ordering information  
Functional Block Diagram  
LBO  
ADV  
INTERNAL  
ADDRESS  
CEN  
256K x 36/  
512K x 18-  
BIT  
MEMORY  
ARRAY  
CLK  
2
Burst  
Logic  
18/19  
Binary  
Counter  
ADSC  
A0*  
A1*  
Q0  
Q1  
CLR  
ADSP  
2
CLK EN  
A0,A1  
A2 - A18  
ADDRESS  
REGISTER  
A0–A  
17/18  
36/18  
36/18  
18/19  
GW  
BWE  
Byte 1  
Write Register  
Byte 1  
Write Driver  
BW  
1
9
9
Byte 2  
Write Register  
Byte 2  
Write Driver  
BW2  
Byte 3  
Write Register  
Byte 3  
Write Driver  
BW  
3
9
9
Byte 4  
Write Register  
Byte 4  
Write Driver  
BW4  
CE  
Q
D
CS0  
Enable  
Register  
CLK EN  
DATA INPUT  
REGISTER  
CS  
1
ZZ  
Powerdown  
OE  
OUTPUT  
BUFFER  
OE  
,
36/18  
I/O0  
I/OP1–I/OP4  
–I/O31  
5309 drw 01  
DECEMBER 2014  
1
©2014 Integrated Device Technology, Inc.  
DSC-5309/06  
1234567...20

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 		3.3V Synchronous SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs, Single Cycle Deselect
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 		3.3V Synchronous SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs, Single Cycle Deselect

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