Datasheet > 71V67803

71V67803

更新时间： 2023-12-20 18:45:09

品牌	Logo	应用领域
瑞萨 - RENESAS		静态存储器
页数	文件大小	规格书
23页	297K
描述
3.3V 512K x 18 Synchronous 3.3V I/O PipeLined SRAM

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数据手册

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71V67803 数据手册

256K X 36, 512K X 18

3.3VSynchronousSRAMs

3.3V I/O, Burst Counter

71V67603

71V67803

PipelinedOutputs,SingleCycleDeselect

Features

◆

256K x 36, 512K x 18 memory configurations

Supports high system speed:

LBO input selects interleaved or linear burst mode

3.3V core power supply

Power down controlled by ZZ input

3.3V I/O supply (VDDQ)

Packaged in a JEDEC Standard 100-pin thin plastic quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch

ball grid array (fBGA).

◆

– 166MHz 3.5ns clock access time

– 150MHz 3.8ns clock access time

– 133MHz 4.2ns clock access time

Self-timed write cycle with global write control (GW), byte

write enable (BWE), and byte writes (BWx)

◆

FunctionalBlockDiagram

LBO

ADV

INTERNAL

ADDRESS

Burst

Sequence

CEN

256K x 36/

512K x 18-

BIT

MEMORY

ARRAY

CLK

Burst

Logic

18/19

Binary

Counter

ADSC

A0*

A1*

CLR

ADSP

CLK EN

A0,A1

A2–A18

A0–A17/18

ADDRESS

36/18

18/19

Byte 1

Write Register

BWE

Byte 1

Write Driver

Byte 2

Write Register

Byte 2

Write Driver

BW2

Byte 3

Write Register

Byte 3

Write Driver

Byte 4

Write Register

Byte 4

Write Driver

BW4

OUTPUT

Enable

DATA INPUT

CLK EN

Powerdown

Enable

Delay

OUTPUT

BUFFER

36/18

I/O

–I/O31

I/OP1–I/OP4

5301 drw 01

Sep.13.21

12 3 4 5 6 7...23

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