128K x 36, 3.3V Synchronous IDT71V546S/XS
SRAM with ZBT™ Feature,
Burst Counter and Pipelined Outputs
Features
◆
128K x 36 memory configuration, pipelined outputs
Supports high performance system speed - 133 MHz
(4.2 ns Clock-to-Data Access)
clockcycle,andtwocycles laterits associateddatacycleoccurs,beit
read or write.
TheIDT71V546containsdataI/O,addressandcontrolsignalregis-
ters. Outputenableistheonlyasynchronoussignalandcanbeusedto
disabletheoutputsatanygiventime.
AClockEnable (CEN)pinallows operationofthe IDT71V546tobe
suspended as long as necessary. All synchronous inputs are ignored
whenCENishighandtheinternaldeviceregisterswillholdtheirprevious
values.
Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser
todeselectthedevicewhendesired. Ifanyoneofthesethreeisnotactive
whenADV/LDislow,nonewmemoryoperationcanbeinitiatedandany
burst that was in progress is stopped. However, any pending data
transfers(readsorwrites)willbecompleted. Thedatabuswilltri-statetwo
cyclesafterthechipisdeselectedorawriteinitiated.
◆
◆
◆
ZBTTM Feature - No dead cycles between write and read
cycles
Internally synchronized registered outputs eliminate the
need to control OE
◆
◆
Single R/W (READ/WRITE) control pin
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW1 - BW4) control (May tie active)
Three chip enables for simple depth expansion
Single 3.3V power supply (±5%)
◆
◆
◆
◆
◆
Packaged in a JEDEC standard 100-pin TQFP package
TheIDT71V546hasanon-chipburstcounter. Intheburstmode,the
IDT71V546canprovidefourcyclesofdataforasingleaddresspresented
totheSRAM. TheorderoftheburstsequenceisdefinedbytheLBOinput
pin. TheLBOpinselectsbetweenlinearandinterleavedburstsequence.
The ADV/LD signalis usedtoloada newexternaladdress (ADV/LD =
LOW) orincrementtheinternalburstcounter(ADV/LD =HIGH).
TheIDT71V546SRAMutilizesIDT'shigh-performance,high-volume
3.3V CMOS process, and is packaged in a JEDEC standard 14mm x
20mm100-pinthinplasticquadflatpack(TQFP)forhighboarddensity.
Description
The IDT71V546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)
synchronous SRAM organized as 128K x 36 bits. It is designed to
eliminatedeadbuscycleswhenturningthebusaroundbetweenreads
TM
andwrites,orwritesandreads. ThusithasbeengiventhenameZBT ,
or Zero Bus Turn-around.
Address and control signals are applied to the SRAM during one
PinDescriptionSummary
A0
- A16
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Three Chip Enables
Output Enable
CE1
, CE
2
, CE
2
OE
R/W
Read/Write Signal
Clock Enable
CEN
Individual Byte Write Selects
Clock
BW
1
, BW
2
, BW
3
, BW
4
CLK
ADV/LD
Advance Burst Address / Load New Address
Linear / Interleaved Burst Order
Data Input/Output
Synchronous
Static
LBO
I/O0
- I/O31, I/OP1 - I/OP4
Synchronous
Static
VDD
3.3V Power
Supply
Supply
VSS
Ground
Static
3821 tbl 01
OCTOBER 2008
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.
1
DSC-3821/05
©2007IntegratedDeviceTechnology,Inc.
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