Datasheet > 71V546

71V546

更新时间： 2024-11-28 14:57:19

品牌	Logo	应用领域
瑞萨 - RENESAS		静态存储器
页数	文件大小	规格书
22页	444K
描述
3.3V 128K x 36 ZBT Synchronous PipeLined SRAM

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数据手册

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71V546 数据手册

128K x 36, 3.3V Synchronous

IDT71V546S

SRAM with ZBT™ Feature

Burst Counter and Pipelined Outputs

Features

◆

128K x 36 memory configuration, pipelined outputs

Supports high performance system speed - 133 MHz

(4.2 ns Clock-to-Data Access)

Positive clock-edge triggered address, data, and control

signal registers for fully pipelined applications

4-word burst capability (interleaved or linear)

Individual byte write (BW1 - BW4) control (May tie active)

Three chip enables for simple depth expansion

Single 3.3V power supply (±5%)

◆

ZBT^TMFeature - No dead cycles between write and read

cycles

Internally synchronized registered outputs eliminate the

need to control OE

Packaged in a JEDEC standard 100-pin TQFP package

Green parts available, see Ordering Information

Single R/W (READ/WRITE) control pin

FunctionalBlockDiagram

128K x 36 BIT

MEMORY ARRAY

LBO

Address A [0:16]

Address

CE1, CE2, CE2

R/W

CEN

Control

ADV/LD

BWx

Control Logic

Clk

Mux

Sel

Output Register

Clock

Gate

3821 drw 01

Data I/O [0:31], I/O P[1:4]

AUGUST 2017

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.

DSC-3821/07

12 3 4 5 6 7...22

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