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71V432S7PFGI PDF预览

71V432S7PFGI

更新时间: 2024-11-27 21:19:55
品牌 Logo 应用领域
艾迪悌 - IDT 时钟静态存储器内存集成电路
页数 文件大小 规格书
18页 1062K
描述
Cache SRAM, 32KX32, 7ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, PLASTIC, MO-136DJ, TQFP-100

71V432S7PFGI 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFP包装说明:14 X 20 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, PLASTIC, MO-136DJ, TQFP-100
针数:100Reach Compliance Code:unknown
ECCN代码:3A991HTS代码:8542.32.00.41
风险等级:5.74最长访问时间:7 ns
其他特性:PIPELINED ARCHITECTURE最大时钟频率 (fCLK):66 MHz
I/O 类型:COMMONJESD-30 代码:R-PQFP-G100
JESD-609代码:e3长度:20 mm
内存密度:1048576 bit内存集成电路类型:CACHE SRAM
内存宽度:32湿度敏感等级:3
功能数量:1端子数量:100
字数:32768 words字数代码:32000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:32KX32
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP100,.63X.87
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.6 mm最大待机电流:0.015 A
最小待机电流:3.14 V子类别:SRAMs
最大压摆率:0.16 mA最大供电电压 (Vsup):3.63 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:14 mmBase Number Matches:1

71V432S7PFGI 数据手册

 浏览型号71V432S7PFGI的Datasheet PDF文件第2页浏览型号71V432S7PFGI的Datasheet PDF文件第3页浏览型号71V432S7PFGI的Datasheet PDF文件第4页浏览型号71V432S7PFGI的Datasheet PDF文件第5页浏览型号71V432S7PFGI的Datasheet PDF文件第6页浏览型号71V432S7PFGI的Datasheet PDF文件第7页 
32Kx32CacheRAM™  
3.3VSynchronousSRAM  
BurstCounter  
IDT71V432  
SingleCycleDeselect  
Features  
processor interfaces. The pipelined burst architecture provides cost-  
effective 3-1-1-1 secondary cache performance for processors up to  
100 MHz.  
32K x 32 memory configuration  
Supports high-performance system speed:  
The IDT71V432 CacheRAM contains write, data, address, and  
controlregisters.InternallogicallowstheCacheRAMtogenerateaself-  
timedwritebaseduponadecisionwhichcanbeleftuntiltheextremeend  
ofthewritecycle.  
CommercialandIndustrial:  
— 5ns Clock-to-DataAccess (100MHz)  
— 6ns Clock-to-DataAccess (83MHz)  
— 7ns Clock-to-DataAccess (66MHz)  
Single-cycle deselect functionality (Compatible with  
Micron Part # MT58LC32K32D7LG-XX)  
LBO input selects interleaved or linear burst mode  
Self-timed write cycle with global write control (GW), byte  
write enable (BWE), and byte writes (BWx)  
Power down controlled by ZZ input  
Theburstmodefeatureoffersthehighestlevelofperformancetothe  
systemdesigner, as the IDT71V432canprovide fourcycles ofdata for  
asingleaddresspresentedtotheCacheRAM.Aninternalburstaddress  
counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe  
accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone  
cycle before it is available on the next rising clock edge. If burst mode  
operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput  
datawillbeavailabletotheuseronthenextthreerisingclockedges.The  
orderofthesethreeaddresseswillbedefinedbytheinternalburstcounter  
andthe LBO inputpin.  
Operates with a single 3.3V power supply (+10/-5%)  
Packaged in a JEDEC Standard 100-pin rectangular plastic  
thin quad flatpack (TQFP).  
TheIDT71V432CacheRAMutilizes IDT's high-performance,high-  
volume 3.3V CMOS process, and is packaged in a JEDEC Standard  
14mmx20mm100-pinthinplasticquadflatpack(TQFP)foroptimumboard  
densityinbothdesktopandnotebookapplications.  
Description  
The IDT71V432 is a 3.3V high-speed 1,048,576-bit CacheRAM  
organizedas32Kx32withfullsupportofthePentium™andPowerPC™  
PinDescriptionSummary  
A0A14  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enable  
CE  
CS  
0, CS  
1
Chips Selects  
Output Enable  
OE  
Global Write Enable  
Byte Write Enable  
Individual Byte Write Selects  
Clock  
GW  
BWE  
BW1, BW2, BW3, BW  
4
CLK  
ADV  
Burst Address Advance  
Address Status (Cache Controller)  
Address Status (Processor)  
Linear / Interleaved Burst Order  
Sleep Mode  
Synchronous  
Synchronous  
Synchronous  
DC  
ADSC  
ADSP  
LBO  
ZZ  
Asynchronous  
Synchronous  
DC  
I/O  
0
–I/O31  
Data Input/Output  
3.3V Power  
VDD  
Power  
Ground  
VSS  
Ground  
DC  
3104 tbl 01  
CacheRAMisatrademarkofIntegratedDeviceTechnology.  
PentiumprocessorisatrademarkofIntelCorp.  
PowerPCisatrademarkofInternationalBusinessMachines,Inc.  
OCTOBER 2008  
1
©2005IntegratedDeviceTechnology,Inc.  
DSC-3104/06  

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