32Kx32CacheRAM™
3.3VSynchronousSRAM
BurstCounter
IDT71V432
SingleCycleDeselect
Features
processor interfaces. The pipelined burst architecture provides cost-
effective 3-1-1-1 secondary cache performance for processors up to
100 MHz.
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32K x 32 memory configuration
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Supports high-performance system speed:
The IDT71V432 CacheRAM contains write, data, address, and
controlregisters.InternallogicallowstheCacheRAMtogenerateaself-
timedwritebaseduponadecisionwhichcanbeleftuntiltheextremeend
ofthewritecycle.
CommercialandIndustrial:
— 5ns Clock-to-DataAccess (100MHz)
— 6ns Clock-to-DataAccess (83MHz)
— 7ns Clock-to-DataAccess (66MHz)
Single-cycle deselect functionality (Compatible with
Micron Part # MT58LC32K32D7LG-XX)
LBO input selects interleaved or linear burst mode
Self-timed write cycle with global write control (GW), byte
write enable (BWE), and byte writes (BWx)
Power down controlled by ZZ input
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Theburstmodefeatureoffersthehighestlevelofperformancetothe
systemdesigner, as the IDT71V432canprovide fourcycles ofdata for
asingleaddresspresentedtotheCacheRAM.Aninternalburstaddress
counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe
accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone
cycle before it is available on the next rising clock edge. If burst mode
operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput
datawillbeavailabletotheuseronthenextthreerisingclockedges.The
orderofthesethreeaddresseswillbedefinedbytheinternalburstcounter
andthe LBO inputpin.
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Operates with a single 3.3V power supply (+10/-5%)
Packaged in a JEDEC Standard 100-pin rectangular plastic
thin quad flatpack (TQFP).
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TheIDT71V432CacheRAMutilizes IDT's high-performance,high-
volume 3.3V CMOS process, and is packaged in a JEDEC Standard
14mmx20mm100-pinthinplasticquadflatpack(TQFP)foroptimumboard
densityinbothdesktopandnotebookapplications.
Description
The IDT71V432 is a 3.3V high-speed 1,048,576-bit CacheRAM
organizedas32Kx32withfullsupportofthePentium™andPowerPC™
PinDescriptionSummary
A0–A14
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Chip Enable
CE
CS
0, CS
1
Chips Selects
Output Enable
OE
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
Clock
GW
BWE
BW1, BW2, BW3, BW
4
CLK
ADV
Burst Address Advance
Address Status (Cache Controller)
Address Status (Processor)
Linear / Interleaved Burst Order
Sleep Mode
Synchronous
Synchronous
Synchronous
DC
ADSC
ADSP
LBO
ZZ
Asynchronous
Synchronous
DC
I/O
0
–I/O31
Data Input/Output
3.3V Power
VDD
Power
Ground
VSS
Ground
DC
3104 tbl 01
CacheRAMisatrademarkofIntegratedDeviceTechnology.
PentiumprocessorisatrademarkofIntelCorp.
PowerPCisatrademarkofInternationalBusinessMachines,Inc.
OCTOBER 2008
1
©2005IntegratedDeviceTechnology,Inc.
DSC-3104/06