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71V432S5PFI

更新时间: 2024-11-28 05:03:23
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器
页数 文件大小 规格书
18页 1062K
描述
Cache SRAM, 32KX32, 5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MO-136DJ, TQFP-100

71V432S5PFI 数据手册

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32Kx32CacheRAM™  
3.3VSynchronousSRAM  
BurstCounter  
IDT71V432  
SingleCycleDeselect  
Features  
processor interfaces. The pipelined burst architecture provides cost-  
effective 3-1-1-1 secondary cache performance for processors up to  
100 MHz.  
32K x 32 memory configuration  
Supports high-performance system speed:  
The IDT71V432 CacheRAM contains write, data, address, and  
controlregisters.InternallogicallowstheCacheRAMtogenerateaself-  
timedwritebaseduponadecisionwhichcanbeleftuntiltheextremeend  
ofthewritecycle.  
CommercialandIndustrial:  
— 5ns Clock-to-DataAccess (100MHz)  
— 6ns Clock-to-DataAccess (83MHz)  
— 7ns Clock-to-DataAccess (66MHz)  
Single-cycle deselect functionality (Compatible with  
Micron Part # MT58LC32K32D7LG-XX)  
LBO input selects interleaved or linear burst mode  
Self-timed write cycle with global write control (GW), byte  
write enable (BWE), and byte writes (BWx)  
Power down controlled by ZZ input  
Theburstmodefeatureoffersthehighestlevelofperformancetothe  
systemdesigner, as the IDT71V432canprovide fourcycles ofdata for  
asingleaddresspresentedtotheCacheRAM.Aninternalburstaddress  
counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe  
accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone  
cycle before it is available on the next rising clock edge. If burst mode  
operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput  
datawillbeavailabletotheuseronthenextthreerisingclockedges.The  
orderofthesethreeaddresseswillbedefinedbytheinternalburstcounter  
andthe LBO inputpin.  
Operates with a single 3.3V power supply (+10/-5%)  
Packaged in a JEDEC Standard 100-pin rectangular plastic  
thin quad flatpack (TQFP).  
TheIDT71V432CacheRAMutilizes IDT's high-performance,high-  
volume 3.3V CMOS process, and is packaged in a JEDEC Standard  
14mmx20mm100-pinthinplasticquadflatpack(TQFP)foroptimumboard  
densityinbothdesktopandnotebookapplications.  
Description  
The IDT71V432 is a 3.3V high-speed 1,048,576-bit CacheRAM  
organizedas32Kx32withfullsupportofthePentium™andPowerPC™  
PinDescriptionSummary  
A0A14  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enable  
CE  
CS  
0, CS  
1
Chips Selects  
Output Enable  
OE  
Global Write Enable  
Byte Write Enable  
Individual Byte Write Selects  
Clock  
GW  
BWE  
BW1, BW2, BW3, BW  
4
CLK  
ADV  
Burst Address Advance  
Address Status (Cache Controller)  
Address Status (Processor)  
Linear / Interleaved Burst Order  
Sleep Mode  
Synchronous  
Synchronous  
Synchronous  
DC  
ADSC  
ADSP  
LBO  
ZZ  
Asynchronous  
Synchronous  
DC  
I/O  
0
–I/O31  
Data Input/Output  
3.3V Power  
VDD  
Power  
Ground  
VSS  
Ground  
DC  
3104 tbl 01  
CacheRAMisatrademarkofIntegratedDeviceTechnology.  
PentiumprocessorisatrademarkofIntelCorp.  
PowerPCisatrademarkofInternationalBusinessMachines,Inc.  
OCTOBER 2008  
1
©2005IntegratedDeviceTechnology,Inc.  
DSC-3104/06  

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