Datasheet > 71V2546

71V2546

更新时间： 2023-12-20 18:46:04

品牌	Logo	应用领域
瑞萨 - RENESAS		静态存储器
页数	文件大小	规格书
22页	280K
描述
3.3V 128Kx36 ZBT Synchronous PipeLined SRAM with 2.5V I/O

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71V2546 数据手册

71V2546S

128K x 36

3.3V Synchronous ZBT™ SRAM

2.5V I/O, Burst Counter

Pipelined Outputs

Features

◆

4-word burst capability (interleaved or linear)

128K x 36 memory configurations

◆

Individual byte write (BW1 - BW4) control (May tie active)

Three chip enables for simple depth expansion

3.3V power supply (±5%), 2.5V I/O Supply (VDDQ)

Packaged in a JEDEC standard 100-pin plastic thin quad

flatpack (TQFP) and 119 ball grid array (BGA)

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

Supports high performance system speed - 150 MHz

(3.8 ns Clock-to-Data Access)

ZBT^TMFeature - No dead cycles between write and read

◆

cycles

◆

Internally synchronized output buffer enable eliminates the

◆

need to control OE

Single R/W (READ/WRITE) control pin

Positive clock-edge triggered address, data, and control

◆

Green parts available, see ordering information

signal registers for fully pipelined applications

FunctionalBlockDiagram

LBO

128Kx36 BIT

MEMORY ARRAY

Address A [0:16]

Address

CE1,CE, CE2

R/W

Control

CEN

ADV/LD

BWx

Control Logic

Clk

Mux

Sel

Output Register

Clock

Gate

5294 drw 01a

Data I/O [0:31],

I/O P[1:4]

ZBT and ZeroBus Turnaround are trademarks of Renesas and the architecture is supported by Micron Technology and Motorola Inc.

Aug.12.20

12 3 4 5 6 7...22

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