Datasheet > 71T75902

71T75902

更新时间： 2023-12-20 18:44:57

品牌	Logo	应用领域
瑞萨 - RENESAS		静态存储器
页数	文件大小	规格书
24页	295K
描述
2.5V 1M x 18 ZBT Synchronous 2.5V I/O Flow-through SRAM

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数据手册

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71T75902 数据手册

71T75902

1M x 18

2.5V Synchronous ZBT™ SRAM

2.5V I/O, Burst Counter

Flow-Through Outputs

◆

Features

Three chip enables for simple depth expansion

2.5V power supply (±5%)

◆

1M x 18 memory configuration

◆

Supports high performance system speed - 100 MHz

2.5V (±5%) I/O Supply (VDDQ)

Power down controlled by ZZ input

Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)

Packaged in a JEDEC standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA)

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

Green parts available, see Ordering Information

(7.5 ns Clock-to-Data Access)

◆

ZBT^TMFeature - No dead cycles between write and read cycles

◆

Internally synchronized output buffer enable eliminates the

need to control OE

Single R/W (READ/WRITE) control pin

4-word burst capability (Interleaved or linear)

Individual byte write (BW1 - BW2 control (May tie active)

◆

Functional Block Diagram — 1M x 18

LBO

1M x 18 BIT

MEMORY ARRAY

Address

Address A [0:19]

CE1,

_2,CE

R/W

Control

CEN

ADV/LD

BWx

Control Logic

Clk

Mux

Sel

Clock

Gate

TMS

Data I/O [0:15], I/O P[1:2]

TDI

TCK

5319 drw 01a

TDO

JTAG

TRST

(optional)

Apr.07.20

12 3 4 5 6 7...24

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