IDT71V3556S/XS
IDT71V3558S/XS
IDT71V3556SA/XSA
IDT71V3558SA/XSA
128K x 36, 256K x 18
3.3VSynchronousZBTSRAMs
3.3V I/O, Burst Counter
PipelinedOutputs
Description
Features
◆
TheIDT71V3556/58are3.3Vhigh-speed4,718,592-bit(4.5Mega-
bit) synchronous SRAMS. They are designed to eliminate dead bus
cycles when turning the bus around between reads and writes, or
writes and reads. Thus, they have been given the name ZBTTM, or
Zero Bus Turnaround.
128K x 36, 256K x 18 memory configurations
◆
Supports high performance system speed - 200 MHz
(3.2 ns Clock-to-Data Access)
ZBTTM Feature - No dead cycles between write and read
◆
cycles
◆
Address and control signals are applied to the SRAM during one
clockcycle,andtwocycleslatertheassociateddatacycleoccurs,beit
read or write.
The IDT71V3556/58 contain data I/O, address and control signal
registers.Outputenableistheonlyasynchronoussignalandcanbeused
todisabletheoutputsatanygiventime.
A Clock Enable (CEN) pin allows operation of the IDT71V3556/58
to be suspended as long as necessary. All synchronous inputs are
ignored when (CEN) is high and the internal device registers will hold
their previous values.
Internally synchronized output buffer enable eliminates the
need to control OE
Single R/W (READ/WRITE) control pin
Positive clock-edge triggered address, data, and control
◆
◆
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW1 - BW4) control (May tie active)
Three chip enables for simple depth expansion
3.3V power supply (±5%), 3.3V I/O Supply (VDDQ)
Optional- Boundary Scan JTAG Interface (IEEE 1149.1
◆
◆
◆
◆
◆
Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser
to deselect the device when desired. If any one of these three are not
asserted when ADV/LD is low, no new memory operation can be
initiated. However, any pending data transfers (reads or writes) will be
completed.Thedatabuswilltri-statetwocyclesafterchipisdeselected
orawriteisinitiated.
compliant)
◆
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA)
PinDescriptionSummary
A
0
-A17
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Chip Enables
CE
1, CE
2
, CE
2
Output Enable
OE
R/W
Read/Write Signal
Clock Enable
CEN
Individual Byte Write Selects
Clock
BW
1, BW
2
, BW
3
, BW
4
CLK
ADV/LD
LBO
TMS
TDI
Advance burst address / Load new address
Linear / Interleaved Burst Order
Test Mode Select
Test Data Input
Synchronous
Static
Synchronous
Synchronous
N/A
TCK
Test Clock
TDO
TRST
ZZ
Test Data Output
Synchronous
Asynchronous
Synchronous
Synchronous
Static
JTAG Reset (Optional)
Sleep Mode
I/O
0-I/O31, I/OP1-I/OP4
Data Input / Output
Core Power, I/O Power
Ground
V
V
DD, VDDQ
SS
Supply
Supply
Static
5281 tbl 01
FEBRUARY 2009
1
©2006IntegratedDeviceTechnology,Inc.
DSC-5281/09
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