Datasheet > 71421LA20J8

71421LA20J8

更新时间： 2025-09-04 19:04:35

品牌	Logo	应用领域
瑞萨 - RENESAS		存储
页数	文件大小	规格书
19页	475K
描述
存储容量(Mb):16Kb（2K x 8）;内存数据长度(bit):2K ;字编码数(k):2K ;元器件封装:52-PLCC（19.13x19.13）;

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中文翻译

获取价格

数据手册

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71421LA20J8 数据手册

HIGH SPEED

2K X 8 DUAL-PORT

STATIC RAM

71321SA/LA

71421SA/LA

WITH INTERRUPTS

Features

◆

MASTER IDT71321 easily expands data bus width to 16-or-

more-bits using SLAVE IDT71421

◆

High-speed access

◆

– Commercial: 20/35/55ns (max.)

– Industrial: 25/55ns (max.)

Low-power operation

On-chip port arbitration logic (IDT71321 only)

BUSY output flag on IDT71321; BUSY input on IDT71421

Fully asynchronous operation from either port

Battery backup operation – 2V data retention (LA only)

TTL-compatible, single 5V ±10% power supply

Available in 52-Pin PLCC, 52-Pin STQFP, 64-Pin TQFP, and

64-Pin STQFP

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

Green parts available, see ordering information

◆

– IDT71321/IDT71421SA

— Active: 325mW (typ.)

— Standby: 5mW (typ.)

– IDT71321/421LA

◆

— Active: 325mW (typ.)

— Standby: 1mW (typ.)

Two INT flags for port-to-port communications

◆

FunctionalBlockDiagram

OER

OEL

R/W

I/O0L- I/O7L

I/O0R-I/O7R

I/O

Control

BUSY ^(1,2)

(1,2)

BUSY

10L

10R

Address

Decoder

MEMORY

ARRAY

Address

Decoder

A0R

ARBITRATION

and

INTERRUPT

LOGIC

R/W

(2)

INT

2691 drw 01

NOTES:

1. IDT71321(MASTER):BUSYisopendrainoutputandrequirespullupresistorof270Ω.

IDT71421 (SLAVE): BUSY is input.

2. Open drain output: requires pullup resistor of 270Ω.

SEPTEMBER 2019

DSC-2691/17

12 3 4 5 6 7...19

中文翻译

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