5秒后页面跳转
7140SA100LGB8 PDF预览

7140SA100LGB8

更新时间: 2024-11-20 07:48:51
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
22页 291K
描述
Dual-Port SRAM

7140SA100LGB8 技术参数

生命周期:Active包装说明:QCCN,
Reach Compliance Code:compliant风险等级:5.08
最长访问时间:100 nsJESD-30 代码:S-XQCC-N48
内存密度:8192 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:8功能数量:1
端子数量:48字数:1024 words
字数代码:1000工作模式:ASYNCHRONOUS
最高工作温度:125 °C最低工作温度:-55 °C
组织:1KX8封装主体材料:UNSPECIFIED
封装代码:QCCN封装形状:SQUARE
封装形式:CHIP CARRIER并行/串行:PARALLEL
筛选级别:MIL-PRF-38535 Class Q最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:NO LEAD
端子位置:QUADBase Number Matches:1

7140SA100LGB8 数据手册

 浏览型号7140SA100LGB8的Datasheet PDF文件第2页浏览型号7140SA100LGB8的Datasheet PDF文件第3页浏览型号7140SA100LGB8的Datasheet PDF文件第4页浏览型号7140SA100LGB8的Datasheet PDF文件第5页浏览型号7140SA100LGB8的Datasheet PDF文件第6页浏览型号7140SA100LGB8的Datasheet PDF文件第7页 
IDT7130SA/LA  
IDT7140SA/LA  
HIGH SPEED  
1K X 8 DUAL-PORT  
STATIC SRAM  
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018  
Features  
On-chip port arbitration logic (IDT7130 Only)  
BUSY output flag on IDT7130; BUSY input on IDT7140  
INT flag for port-to-port communication  
Fully asynchronous operation from either port  
Battery backup operation–2V data retention (LA only)  
TTL-compatible, single 5V ±10% power supply  
Military product compliant to MIL-PRF-38535 QML  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
High-speed access  
– Commercial: 20/25/35/55/100ns (max.)  
– Industrial: 25/55/100ns (max.)  
– Military: 25/35/55/100ns (max.)  
Low-power operation  
– IDT7130/IDT7140SA  
Active: 550mW (typ.)  
Standby: 5mW (typ.)  
– IDT7130/IDT7140LA  
Active: 550mW (typ.)  
Standby: 1mW (typ.)  
Available in 48-pin DIP, LCC and Ceramic Flatpack, 52-pin  
PLCC, and 64-pin STQFP and TQFP  
Green parts available, see ordering information  
MASTER IDT7130 easily expands data bus width to 16-or-  
more-bits using SLAVE IDT7140  
Functional Block Diagram  
OER  
OEL  
CE  
R/W  
L
CE  
R
R/W  
L
R
,
I/O0L- I/O7L  
I/O0R-I/O7R  
(1,2)  
I/O  
Control  
I/O  
Control  
(1,2)  
BUSY  
L
BUSYR  
A
9L  
0L  
A
9R  
0R  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A
A
10  
10  
ARBITRATION  
and  
INTERRUPT  
LOGIC  
CE  
L
L
CE  
OE  
R/W  
R
R
OE  
R
R/W  
L
(2)  
(2)  
INT  
R
INTL  
2689 drw 01  
NOTES:  
1. IDT7130 (MASTER): BUSY is open drain output and requires pullup resistor.  
IDT7140 (SLAVE): BUSY is input.  
2. Open drain output: requires pullup resistor.  
FEBRUARY 2018  
1
DSC-2689/18  

与7140SA100LGB8相关器件

型号 品牌 获取价格 描述 数据表
7140SA100LGI IDT

获取价格

Dual-Port SRAM
7140SA100LGI8 IDT

获取价格

Dual-Port SRAM
7140SA100PB IDT

获取价格

Dual-Port SRAM, 1KX8, 100ns, CMOS, PDIP48, PLASTIC, DIP-48
7140SA100PDG IDT

获取价格

Dual-Port SRAM, 1KX8, 100ns, CMOS, PDIP48, 0.550 X 0.610 INCH, 0.190 INCH HEIGHT, GREEN, P
7140SA100PDGB IDT

获取价格

Dual-Port SRAM, 1KX8, 100ns, CMOS, PDIP48, 0.550 X 0.610 INCH, 0.190 INCH HEIGHT, GREEN, P
7140SA100PDGB8 IDT

获取价格

Dual-Port SRAM, 1KX8, 100ns, CMOS, PDIP48
7140SA100PDGI IDT

获取价格

Dual-Port SRAM, 1KX8, 100ns, CMOS, PDIP48, 0.550 X 0.610 INCH, 0.190 INCH HEIGHT, GREEN, P
7140SA100PFB IDT

获取价格

Dual-Port SRAM, 1KX8, 100ns, CMOS, PQFP64, TQFP-64
7140SA100PFG IDT

获取价格

Dual-Port SRAM, 1KX8, 100ns, CMOS, PQFP64, 14 X 14 MM, 1.40 MM HEIGHT, GREEN, TQFP-64
7140SA100PFG8 IDT

获取价格

Dual-Port SRAM, 1KX8, 100ns, CMOS, PQFP64, TQFP-64