Datasheet > 7140LA55JG

7140LA55JG

更新时间： 2024-11-20 10:47:07

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
22页	291K
描述
Dual-Port SRAM, 1KX8, 55ns, CMOS, PQCC52, 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, GREEN, PLASTIC, LCC-52

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中文翻译

获取价格

数据手册

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7140LA55JG 数据手册

IDT7130SA/LA

IDT7140SA/LA

HIGH SPEED

1K X 8 DUAL-PORT

STATIC SRAM

LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

Features

◆

On-chip port arbitration logic (IDT7130 Only)

BUSY output flag on IDT7130; BUSY input on IDT7140

INT flag for port-to-port communication

Fully asynchronous operation from either port

Battery backup operation–2V data retention (LA only)

TTL-compatible, single 5V ±10% power supply

Military product compliant to MIL-PRF-38535 QML

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

High-speed access

◆

– Commercial: 20/25/35/55/100ns (max.)

– Industrial: 25/55/100ns (max.)

– Military: 25/35/55/100ns (max.)

Low-power operation

◆

– IDT7130/IDT7140SA

— Active: 550mW (typ.)

— Standby: 5mW (typ.)

– IDT7130/IDT7140LA

— Active: 550mW (typ.)

— Standby: 1mW (typ.)

◆

Available in 48-pin DIP, LCC and Ceramic Flatpack, 52-pin

PLCC, and 64-pin STQFP and TQFP

Green parts available, see ordering information

◆

MASTER IDT7130 easily expands data bus width to 16-or-

more-bits using SLAVE IDT7140

Functional Block Diagram

OER

OEL

R/W

I/O0L- I/O7L

I/O0R-I/O7R

(1,2)

I/O

Control

I/O

Control

(1,2)

BUSY

BUSYR

Address

Decoder

MEMORY

ARRAY

Address

Decoder

ARBITRATION

and

INTERRUPT

LOGIC

R/W

(2)

INT

INTL

2689 drw 01

NOTES:

1. IDT7130 (MASTER): BUSY is open drain output and requires pullup resistor.

IDT7140 (SLAVE): BUSY is input.

2. Open drain output: requires pullup resistor.

FEBRUARY 2018

DSC-2689/18

12 3 4 5 6 7...22

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