Datasheet > 70V7319

70V7319

更新时间： 2023-12-20 18:44:14

品牌	Logo	应用领域
瑞萨 - RENESAS		静态存储器
页数	文件大小	规格书
23页	539K
描述
256K x 18 Synchronous Bank-Switchable Dual-Port SRAM

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数据手册

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70V7319 数据手册

HIGH-SPEED 3.3V 256K x 18

SYNCHRONOUS

BANK-SWITCHABLE

70V7319S

DUAL-PORTSTATICRAM

WITH 3.3V OR 2.5V INTERFACE

Features:

◆

256K x 18 Synchronous Bank-Switchable Dual-ported SRAM

– 1.5ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 200MH

Architecture

– 64 independent 4K x 18 banks

– 4 megabits of memory on chip

Bank access controlled via bank address pins

High-speed data access

– Commercial:3.4ns(200MHz)/3.6ns(166MHz)/

4.2ns(133MHz)(max.)

– Industrial: 4.2ns (133MHz) (max.)

Selectable Pipelined or Flow-Through output mode

Counter enable and repeat features

Dual chip enables allow for depth expansion without

– Data input, address, byte enable and control registers

– Self-timed write allows fast cycle time

Separate byte controls for multiplexed bus and bus match-

ingcompatibility

LVTTL- compatible, 3.3V (±150mV) power supply

for core

LVTTL compatible, selectable 3.3V (±150mV) or 2.5V

(±100mV) power supply for I/Os and control signals on each

port

Industrial temperature range (-40°C to +85°C) is

available at 133MHz

◆

additionallogic

Full synchronous operation on both ports

– 5nscycletime, 200MHzoperation(14Gbpsbandwidth)

– Fast 3.4ns clock to data out

◆

Available in a 208-pin fine pitch Ball Grid Array (fpBGA) and

256-pin Ball Grid Array (BGA)

Supports JTAG features compliant with IEEE 1149.1

Green parts available, see ordering information

◆

FunctionalBlockDiagram

PL/FT

OPT

CLK

ADS

CNTEN

REPEAT

R/W

OPT

CLK

ADS

CNTEN

REPEAT

R/W

CE0L

CE1L

MUX

CONTROL

LOGIC

CONTROL

LOGIC

CE0R

CE1R

4Kx18

MEMORY

ARRAY

(BANK 0)

MUX

I/O

CONTROL

I/O

CONTROL

I/O0L-17L

I/O0R-17R

4Kx18

MEMORY

ARRAY

11R

(BANK 1)

11L

ADDRESS

DECODE

ADDRESS

DECODE

MUX

BA5R

BA4R

BA3R

BA2R

BA1R

BA0R

BA5L

BA4L

BA3L

BA2L

BA1L

BA0L

BANK

DECODE

BANK

DECODE

MUX

4Kx18

MEMORY

ARRAY

(BANK 63)

NOTE:

MUX

1. TheBank-Switchabledual-portusesatrueSRAMcore

insteadofthetraditionaldual-portSRAMcore.Asaresult,it

hasuniqueoperatingcharacteristics.Pleaserefertothe

functionaldescriptiononpage19fordetails.

5629 drw 01

TMS

TCK

TRST

TDI

TDO

JTAG

OCTOBER 2019

DSC 5629/13

12 3 4 5 6 7...23

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