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70V28

更新时间: 2024-11-09 14:57:59
品牌 Logo 应用领域
瑞萨 - RENESAS /
页数 文件大小 规格书
19页 473K
描述
64K x 16 3.3V Dual-Port RAM

70V28 数据手册

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70V28L  
HIGH-SPEED 3.3V  
64K x 16 DUAL-PORT  
STATIC RAM  
Features  
True Dual-Ported memory cells which allow simultaneous  
access of the same memory location  
High-speed access  
M/S = VIH for BUSY output flag on Master,  
M/S = VIL for BUSY input on Slave  
Busy and Interrupt Flags  
On-chip port arbitration logic  
Full on-chip hardware support of semaphore signaling  
between ports  
Fully asynchronous operation from either port  
Separate upper-byte and lower-byte controls for multi-  
plexed bus and bus matching compatibility  
LVTTL-compatible, single 3.3V (±0.3V) power supply  
Available in a 100-pin TQFP  
– Commercial: 15/20ns (max.)  
– Industrial: 20ns (max.)  
Low-power operation  
– IDT70V28L  
Active: 440mW (typ.)  
Standby: 660µW (typ.)  
Dual chip enables allow for depth expansion without  
external logic  
IDT70V28 easily expands data bus width to 32 bits or  
more using the Master/Slave select when cascading more  
than one device  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
Green parts available, see ordering information  
Functional Block Diagram  
R/WL  
R/WR  
UBL  
UBR  
CE0L  
CE0R  
CE1L  
CE1R  
OER  
OEL  
LBR  
LBL  
I/O 8-15L  
I/O8-15R  
I/O0-7R  
I/O  
Control  
I/O  
Control  
0-7L  
I/O  
(1,2)  
(1,2)  
BUSY  
R
BUSY  
L
64Kx16  
MEMORY  
ARRAY  
70V28  
15L  
A
15R  
0R  
A
Address  
Decoder  
Address  
Decoder  
A
0L  
A
16  
16  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE0R  
CE0L  
CE1L  
OEL  
CE1R  
OER  
R/W  
L
R/WR  
SEM  
L
(2)  
SEM  
R
(2)  
INTR  
INT  
L
M/S(1)  
NOTES:  
4849 drw 01  
1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).  
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).  
JUNE 2019  
1
DSC-4849/8  

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