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70V05L35JG8 PDF预览

70V05L35JG8

更新时间: 2024-11-12 18:53:07
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
22页 162K
描述
Application Specific SRAM, 8KX8, 35ns, CMOS, PQCC68

70V05L35JG8 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active包装说明:QCCJ, LDCC68,1.0SQ
Reach Compliance Code:compliant风险等级:5.24
最长访问时间:35 nsI/O 类型:COMMON
JESD-30 代码:S-PQCC-J68JESD-609代码:e0
内存密度:65536 bit内存集成电路类型:APPLICATION SPECIFIC SRAM
内存宽度:8端口数量:2
端子数量:68字数:8192 words
字数代码:8000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:8KX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC68,1.0SQ封装形状:SQUARE
封装形式:CHIP CARRIER并行/串行:PARALLEL
峰值回流温度(摄氏度):225电源:3.3 V
认证状态:Not Qualified最大待机电流:0.0025 A
最小待机电流:3 V子类别:SRAMs
最大压摆率:0.155 mA标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
Base Number Matches:1

70V05L35JG8 数据手册

 浏览型号70V05L35JG8的Datasheet PDF文件第2页浏览型号70V05L35JG8的Datasheet PDF文件第3页浏览型号70V05L35JG8的Datasheet PDF文件第4页浏览型号70V05L35JG8的Datasheet PDF文件第5页浏览型号70V05L35JG8的Datasheet PDF文件第6页浏览型号70V05L35JG8的Datasheet PDF文件第7页 
IDT70V05S/L  
HIGH-SPEED 3.3V  
8K x 8 DUAL-PORT  
STATIC RAM  
Features  
True Dual-Ported memory cells which allow simultaneous  
reads of the same memory location  
High-speed access  
one device  
M/S = VIH for BUSY output flag on Master  
M/S = VIL for BUSY input on Slave  
Interrupt Flag  
On-chip port arbitration logic  
Commercial: 15/20/25/35/55ns (max.)  
Industrial: 20ns (max.)  
Low-power operation  
Full on-chip hardware support of semaphore signaling  
between ports  
IDT70V05S  
Active:400mW(typ.)  
Standby: 3.3mW (typ.)  
IDT70V05L  
Fully asynchronous operation from either port  
TTL-compatible, single 3.3V (±0.3V) power supply  
Available in 68-pin PGA and PLCC, and a 64-pin TQFP  
Industrial temperature range (-40°C to +85°C) is available  
for selected speeds  
Active:380mW(typ.)  
Standby: 660µW (typ.)  
IDT70V05 easily expands data bus width to 16 bits or more  
using the Master/Slave select when cascading more than  
Green parts available, see ordering information  
Functional Block Diagram  
OEL  
OER  
CE  
L
CE  
R/W  
R
R/W  
L
R
,
I/O0L- I/O7L  
I/O0R-I/O7R  
I/O  
Control  
I/O  
Control  
(1,2)  
L
(1,2)  
R
BUSY  
BUSY  
A
12L  
A
12R  
0R  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A
0L  
A
13  
13  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE  
OE  
L
L
CE  
OE  
R/W  
R
R
R
R/W  
L
SEM  
L
SEM  
R
M/S  
(2)  
(2)  
INTL  
INTR  
2942 drw 01  
NOTES:  
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.  
2. BUSY outputs and INT outputs are non-tri-stated push-pull.  
JUNE 2012  
1
DSC 2941/10  
©2012IntegratedDeviceTechnology,Inc.  

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