Datasheet > 70T633S15BCGI

70T633S15BCGI

更新时间： 2022-12-29 21:22:09

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
27页	437K
描述
HIGH-SPEED 2.5V 512/256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM

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70T633S15BCGI 数据手册

IDT70T633/1S

HIGH-SPEED 2.5V

512/256K x 18

ASYNCHRONOUS DUAL-PORT

STATIC RAM

WITH 3.3V 0R 2.5V INTERFACE

Features

◆

Full hardware support of semaphore signaling between

ports on-chip

Fully asynchronous operation from either port

Separate byte controls for multiplexed bus and bus

matching compatibility

Sleep Mode Inputs on both ports

Supports JTAG features compliant to IEEE 1149.1 in

BGA-208 and BGA-256 packages

Single 2.5V (±100mV) power supply for core

LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)

power supply for I/Os and control signals on each port

Available in a 256-ball Ball Grid Array and 208-ball fine pitch

Ball Grid Array

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

Green parts available, see ordering information

◆

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed access

◆

– Commercial:10/12/15ns(max.)

– Industrial: 10/12ns(max.)

RapidWrite Mode simplifies high-speed consecutive write

cycles

Dual chip enables allow for depth expansion without

external logic

IDT70T633/1 easily expands data bus width to 36 bits or

more using the Master/Slave select when cascading more

than one device

◆

M/S = VIH for BUSY output flag on Master,

M/S = VIL for BUSY input on Slave

Busy and Interrupt Flags

◆

On-chip port arbitration logic

Functional Block Diagram

U B

L B

R/W L

R/W R

C E 0L

C E 0R

CE1L

CE1R

OEL

OER

Dout0-8_L

Dout9-17_L

Dout0-8_R

Dout9-17_R

512/256K x 18

MEMORY

ARRAY

Din_L

I/O0L- I/O17L

Din_R

I/O0R - I/O17R

(1)

18R

(1)

Address

Decoder

Address

Decoder

18L

ADDR_L

ADDR_R

TDI

TCK

TMS

JTAG

OER

ARBITRATION

TDO

INTERRUPT

SEMAPHORE

LOGIC

C E 0R

CE1R

C E 0L

CE1L

R/WL

R/W

(2,3)

B U S Y

S EM

INT

B U S Y

S E M

M/S

(3)

IN T

CONTROL

LOGIC

(4)

ZZR

NOTES:

1. Address A18x is a NC for IDT70T631.

5670 drw 01

2. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).

BUSY and INT are non-tri-state totem-pole outputs (push-pull).

4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the

sleep mode pins themselves (ZZx) are not affected during sleep mode.

JUNE 2012

DSC-5670/9

12 3 4 5 6 7...27

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