Datasheet > 70T633

70T633

更新时间： 2024-09-19 14:57:35

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
28页	529K
描述
512K x 18, 3.3V/2.5V Dual-Port RAM, Interleaved I/O's

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中文翻译

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数据手册

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70T633 数据手册

70T633/1S

HIGH-SPEED 2.5V

512/256K x 18

ASYNCHRONOUS DUAL-PORT

STATIC RAM

WITH 3.3V 0R 2.5V INTERFACE

Features

◆

Full hardware support of semaphore signaling between

ports on-chip

Fully asynchronous operation from either port

Separate byte controls for multiplexed bus and bus

matching compatibility

Sleep Mode Inputs on both ports

Supports JTAG features compliant to IEEE 1149.1 in

BGA-208 and BGA-256 packages

Single 2.5V (±100mV) power supply for core

LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)

power supply for I/Os and control signals on each port

Available in a 256-ball Ball Grid Array and 208-ball fine pitch

Ball Grid Array

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

Green parts available, see ordering information

◆

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed access

◆

– Commercial:10/12/15ns(max.)

– Industrial:10/12ns(max.)

RapidWrite Mode simplifies high-speed consecutive write

◆

cycles

◆

Dual chip enables allow for depth expansion without

◆

external logic

◆

IDT70T633/1 easily expands data bus width to 36 bits or

more using the Master/Slave select when cascading more

than one device

M/S = VIH for BUSY output flag on Master,

◆

M/S = VIL for BUSY input on Slave

Busy and Interrupt Flags

On-chip port arbitration logic

◆

Functional Block Diagram

LBL

R/WR

CE0L

CE0R

CE1L

CE1R

OEL

OER

Dout0-8_L

Dout9-17_L

Dout0-8_R

Dout9-17_R

512/256K x 18

MEMORY

ARRAY

Din_L

I/O0L- I/O17L

Din_R

I/O0R - I/O17R

(1)

18R

(1)

Address

Decoder

Address

Decoder

18L

ADDR_L

ADDR_R

TDI

TCK

TMS

TRST

JTAG

ARBITRATION

TDO

INTERRUPT

SEMAPHORE

LOGIC

CE0R

CE1R

CE0L

CE1L

R/WL

R/W

(2,3)

BUSY

SEM

INT

BUSY

SEM

M/S

(3)

INT

CONTROL

LOGIC

(4)

ZZR

NOTES:

1. Address A18x is a NC for IDT70T631.

5670 drw 01

2. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).

BUSY and INT are non-tri-state totem-pole outputs (push-pull).

4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the

sleep mode pins themselves (ZZx) are not affected during sleep mode.

AUGUST 2019

DSC-5670/11

12 3 4 5 6 7...28

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与70T633相关器件

型号	品牌	获取价格	描述	数据表
70T633S10BCG	IDT	获取价格	HIGH-SPEED 2.5V 512/256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM
70T633S10BCG8	IDT	获取价格	HIGH-SPEED 2.5V 512/256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM
70T633S10BCGI	IDT	获取价格	HIGH-SPEED 2.5V 512/256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM
70T633S10BCGI8	IDT	获取价格	HIGH-SPEED 2.5V 512/256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM
70T633S10BFG	IDT	获取价格	HIGH-SPEED 2.5V 512/256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM
70T633S10BFG8	IDT	获取价格	HIGH-SPEED 2.5V 512/256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM
70T633S10BFGI	IDT	获取价格	HIGH-SPEED 2.5V 512/256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM
70T633S10BFGI8	IDT	获取价格	HIGH-SPEED 2.5V 512/256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM
70T633S10DD	IDT	获取价格	Dual-Port SRAM, 512KX18, 10ns, CMOS, PQFP144, 20 X 20 MM, 1.40 MM HEIGHT, TQFP-144
70T633S10DD8	IDT	获取价格	Multi-Port SRAM, 512KX18, 10ns, CMOS, PQFP144

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