Datasheet > 70T3539M

70T3539M

更新时间： 2023-12-20 18:44:05

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
27页	659K
描述
512K x 36 Sync, 3.3V/2.5V Dual-Port RAM, Interleaved I/O's

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中文翻译

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数据手册

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70T3539M 数据手册

70T3539M

HIGH-SPEED 2.5V

512K x 36

SYNCHRONOUS

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

Features:

◆

– Data input, address, byte enable and control registers

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed data access

– Self-timedwriteallowsfastcycletime

Separate byte controls for multiplexed bus and bus

matching compatibility

Dual Cycle Deselect (DCD) for Pipelined Output Mode

2.5V (±100mV) power supply for core

LVTTL compatible, selectable 3.3V (±150mV) or 2.5V

(±100mV) power supply for I/Os and control signals on

each port

Includes JTAG functionality

Industrial temperature range (-40°C to +85°C) is

available at 133MHz

Available in a 256-pin Ball Grid Array (BGA)

Green parts available, see ordering information

◆

– Commercial: 3.6ns (166MHz)/4.2ns (133MHz)(max.)

– Industrial: 4.2ns (133MHz) (max.)

Selectable Pipelined or Flow-Through output mode

Counter enable and repeat features

Dual chip enables allow for depth expansion without

additional logic

Interrupt and Collision Detection Flags

Full synchronous operation on both ports

– 6ns cycle time, 166MHz operation (12Gbps bandwidth)

– Fast 3.6ns clock to data out

◆

– 1.5ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 166MHz

FunctionalBlockDiagram

BE3R

BE3L

BE2L

BE1L

BE0L

BE2R

BE1R

BE0R

FT/PIPE

0a 1a

0b 1b

0c 1c

0d 1d

1d 0d

1c 0c

1b 0b

1a 0a

FT/PIPER

1/0

R/WL

R/WR

CE0L

CE0R

CE1R

CE1L

B B B

1/0

W W W W W

W W

Dout0-8_L

Dout0-8_R

Dout9-17_L

Dout18-26_L

Dout27-35_L

Dout9-17_R

Dout18-26_R

Dout27-35_R

1d 0d 1c 0c

1b 0b 1a 0a

0a 1a 0b 1b

0c 1c 0d 1d

d c b a

0/1

FT/PIPER

FT/PIPE

a bc d

512K x 36

MEMORY

ARRAY

I/O0L - I/O35L

I/O0R - I/O35R

Din_L

Din_R

CLK

18R

18L

Counter/

Address

Reg.

Counter/

Address

Reg.

REPEAT

ADS

ADDR_R

ADDR_L

REPEAT

ADS

CNTEN

TDI

TCK

TMS

T RST

INTERRUPT

CE0

CE1

JTAG

COLLISION

DETECTION

LOGIC

CE1

TDO

R/W

COL

INT_L

COL_R

INT_R

(1)

ZZR

CONTROL

LOGIC

5678 drw 01

NOTE:

1. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx and

the sleep mode pins themselves (ZZx) are not affected during sleep mode.

JUNE 2019

DSC 5678/10

12 3 4 5 6 7...27

中文翻译

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与70T3539M相关器件

型号	品牌	获取价格	描述	数据表
70T3539MS133BCG	IDT	获取价格	HIGH-SPEED 2.5V 512K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM
70T3539MS133BCG8	IDT	获取价格	Application Specific SRAM, 512KX36, 15ns, CMOS, PBGA256
70T3539MS133BCGI	IDT	获取价格	HIGH-SPEED 2.5V 512K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM
70T3539MS133BCGI8	IDT	获取价格	Application Specific SRAM, 512KX36, 15ns, CMOS, PBGA256
70T3539MS166BCG	IDT	获取价格	HIGH-SPEED 2.5V 512K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM
70T3539MS166BCG8	IDT	获取价格	Dual-Port SRAM, 512KX36, 12ns, CMOS, PBGA256, BGA-256
70T3539MS166BCGI	IDT	获取价格	HIGH-SPEED 2.5V 512K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM
70T3539MS166BCGI8	IDT	获取价格	HIGH-SPEED 2.5V 512K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM
70T3589	RENESAS	获取价格	64K x 36 Sync, 3.3V/2.5V Dual-Port RAM, Interleaved I/O's
70T3589S133BCG	IDT	获取价格	HIGH-SPEED 2.5V 256/128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM

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