Datasheet > 70T3509M

70T3509M

更新时间： 2023-12-20 18:45:25

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
24页	350K
描述
1024K x 36 Sync, 3.3V/2.5V Dual-Port RAM

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中文翻译

获取价格

数据手册

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70T3509M 数据手册

HIGH-SPEED 2.5V

1024K x 36

70T3509M

SYNCHRONOUS

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

Features:

– Data input, address, byte enable and control registers

– Self-timedwriteallowsfastcycletime

Separate byte controls for multiplexed bus and bus

matching compatibility

Dual Cycle Deselect (DCD) for Pipelined Output Mode

2.5V (±100mV) power supply for core

LVTTL compatible, selectable 3.3V (±150mV) or 2.5V

(±100mV) power supply for I/Os and control signals on

each port

◆

True Dual-Port memory cells which allow simultaneous

◆

access of the same memory location

High-speed data access

◆

– Commercial: 4.2ns (133MHz)(max.)

– Industrial: 4.2ns (133MHz)(max.)

Selectable Pipelined or Flow-Through output mode

Counter enable and repeat features

Interrupt Flags

◆

Includes JTAG functionality

Full synchronous operation on both ports

Available in a 256-pin Ball Grid Array (BGA)

Common BGA footprint provides design flexibility over

seven density generations (512K to 36M-bit)

Green parts available, see ordering information

– 7.5nscycletime, 133MHzoperation(9.5Gbpsbandwidth)

– 1.5ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 133MHz

◆

– Fast 4.2ns clock to data out

FunctionalBlockDiagram

BE3R

BE3L

BE2L

BE1L

BE0L

BE2R

BE1R

BE0R

FT/PIPE

0a 1a

0b 1b

0c 1c

0d 1d

1d 0d

1c 0c

1b 0b

1a 0a

FT/PIPER

1/0

R/W

R/WR

(2)

CE0L

CE0R

CE1R

CE1L

1/0

W W W W W W W

OER

OEL

Dout0-8_L

Dout0-8_R

Dout9-17_L

Dout18-26_L

Dout27-35_L

Dout9-17_R

Dout18-26_R

Dout27-35_R

1d 0d 1c 0c

1b 0b 1a 0a

0a 1a 0b 1b

0c 1c 0d 1d

d c b a

0/1

FT/PIPE

FT/PIPER

abcd

1024K x 36

MEMORY

ARRAY

I/O0L - I/O35L

I/O0R - I/O35R

Din_L

Din_R

CLKR

CLK

19R

19L

Counter/

Address

Reg.

Counter/

Address

Reg.

REPEAT

ADS

CNTEN

ADDR_R

ADDR_L

REPEAT

ADS

CNTEN

TDI

TCK

TMS

TRST

CE1

JTAG

INTERRUPT

LOGIC

CE1

TDO

R/W

INT_L

INT_R

(1)

ZZR

CONTROL

LOGIC

ZZL

5682 drw 01

NOTES:

1. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx

and the sleep mode pins themselves (ZZx) are not affected during sleep mode.

2. See Truth Table I for Functionality.

Feb.28.22

12 3 4 5 6 7...24

中文翻译

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与70T3509M相关器件

型号	品牌	获取价格	描述	数据表
70T3509M133BPG	IDT	获取价格	Multi-Port SRAM, 1MX36, 4.2ns, CMOS, PBGA256
70T3509M133BPGI	IDT	获取价格	Multi-Port SRAM, 1MX36, 4.2ns, CMOS, PBGA256
70T3509M133BPI	IDT	获取价格	Multi-Port SRAM, 1MX36, 4.2ns, CMOS, PBGA256
70T3509MS133BPG	IDT	获取价格	HIGH-SPEED 2.5V SYNCHRONOUS DUAL-PORT STATIC RAM
70T3509MS133BPG8	IDT	获取价格	HIGH-SPEED 2.5V SYNCHRONOUS DUAL-PORT STATIC RAM
70T3509MS133BPGI	IDT	获取价格	HIGH-SPEED 2.5V SYNCHRONOUS DUAL-PORT STATIC RAM
70T3509MS133BPGI8	IDT	获取价格	HIGH-SPEED 2.5V SYNCHRONOUS DUAL-PORT STATIC RAM
70T3519	RENESAS	获取价格	256K x 36 Sync, 3.3V/2.5V Dual-Port RAM, Interleaved I/O's
70T3519S133BCG	IDT	获取价格	HIGH-SPEED 2.5V 256/128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM
70T3519S133BCG8	IDT	获取价格	HIGH-SPEED 2.5V 256/128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM

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