HIGH-SPEED 2.5V
512/256/128K X 18
SYNCHRONOUS
IDT70T3339/19/99S
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
– 1.5ns setup to clock and 0.5ns hold on all control, data,
and address inputs @ 200MHz
– Self-timedwriteallowsfastcycletime
Separate byte controls for multiplexed bus and bus
matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output Mode
2.5V ( 100mV) power supply for core
LVTTL compatible, selectable 3.3V ( 150mV) or 2.5V
( 100mV) power supply for I/Os and control signals on
each port
Industrial temperature range (-40°C to +85°C) is
available at 166MHz and 133MHz
Available in a 256-pin Ball Grid Array (BGA) and 208-pin fine
pitch Ball Grid Array (fpBGA)
Supports JTAG features compliant with IEEE 1149.1
Green parts available, see ordering information
Features:
◆
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed data access
◆
◆
– Commercial: 3.4 (200MHz)/3.6ns (166MHz)/
4.2ns (133MHz)(max.)
◆
◆
◆
– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Interrupt and Collision Detection Flags
Full synchronous operation on both ports
– 5ns cycle time, 200MHz operation (14Gbps bandwidth)
– Fast 3.4ns clock to data out
◆
◆
◆
◆
◆
◆
◆
◆
◆
– Data input, address, byte enable and control registers
Functional Block Diagram
UBL
UBR
LBL
LBR
FT/PIPE
L
0a 1a
a
0b 1b
b
1b 0b
b
1a 0a
a
FT/PIPER
1/0
1/0
R/WL
R/W
R
CE0L
CE0R
1
1
CE1R
CE1L
B
B
B B
0
W W
W W
0
0
L
1
L
1
0
R
R
1/0
1/0
Dout0-8_L
Dout9-17_L
Dout0-8_R
Dout9-17_R
OE
L
OER
,
0a 1a
1b 0b 1a 0a
ab
0b
1b
0/1
FT/PIPE
L
0/1
FT/PIPER
ba
512/256/128K x 18
MEMORY
ARRAY
Din_L
I/O0R - I/O17R
I/O0L - I/O17L
Din_R
,
CLK
R
CLK
L
(1)
18R
(1)
18L
A
A
Counter/
Address
Reg.
Counter/
Address
Reg.
A
0L
REPEAT
ADS
CNTEN
A
0R
REPEAT
ADS
CNTEN
ADDR_R
ADDR_L
L
R
R
L
R
L
TDI
TCK
TMS
INTERRUPT
CE
0
R
R
CE
0
JTAG
L
COLLISION
DETECTION
LOGIC
CE1
TRST
TDO
CE1
L
R/W
R
R/W
L
COL
L
COL
R
INT
L
INTR
5652 drw 01
(2)
(2)
ZZR
ZZ
ZZ
L
CONTROL
LOGIC
NOTES:
1. Address A18 is a NC for the IDT70T3319. Also, Addresses A18 and A17 are NC's for the IDT70T3399.
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and
OPTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode.
FEBRUARY 2018
1
DSC-5652/9
©2018 Integrated Device Technology, Inc.