Datasheet > 70T3399S200BCGI8

70T3399S200BCGI8

更新时间： 2024-02-18 21:30:32

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
27页	342K
描述
HIGH-SPEED SYNCHRONOUS DUAL-PORT STATIC RAM

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中文翻译

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数据手册

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70T3399S200BCGI8 数据手册

HIGH-SPEED 2.5V

512/256/128K X 18

SYNCHRONOUS

IDT70T3339/19/99S

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

– 1.5ns setup to clock and 0.5ns hold on all control, data,

and address inputs @ 200MHz

– Self-timedwriteallowsfastcycletime

Separate byte controls for multiplexed bus and bus

matching compatibility

Dual Cycle Deselect (DCD) for Pipelined Output Mode

2.5V ( 100mV) power supply for core

LVTTL compatible, selectable 3.3V ( 150mV) or 2.5V

( 100mV) power supply for I/Os and control signals on

each port

Industrial temperature range (-40°C to +85°C) is

available at 166MHz and 133MHz

Available in a 256-pin Ball Grid Array (BGA) and 208-pin fine

pitch Ball Grid Array (fpBGA)

Supports JTAG features compliant with IEEE 1149.1

Green parts available, see ordering information

Features:

◆

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed data access

◆

– Commercial: 3.4 (200MHz)/3.6ns (166MHz)/

4.2ns (133MHz)(max.)

◆

– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)

Selectable Pipelined or Flow-Through output mode

Counter enable and repeat features

Dual chip enables allow for depth expansion without

additional logic

Interrupt and Collision Detection Flags

Full synchronous operation on both ports

– 5ns cycle time, 200MHz operation (14Gbps bandwidth)

– Fast 3.4ns clock to data out

◆

– Data input, address, byte enable and control registers

Functional Block Diagram

UBL

UBR

LBL

LBR

FT/PIPE

0a 1a

0b 1b

1b 0b

1a 0a

FT/PIPER

1/0

R/WL

R/W

CE0L

CE0R

CE1R

CE1L

B B

W W

1/0

Dout0-8_L

Dout9-17_L

Dout0-8_R

Dout9-17_R

OER

0a 1a

1b 0b 1a 0a

0/1

FT/PIPE

0/1

FT/PIPER

512/256/128K x 18

MEMORY

ARRAY

Din_L

I/O0R - I/O17R

I/O0L - I/O17L

Din_R

CLK

(1)

18R

(1)

18L

Counter/

Address

Reg.

Counter/

Address

Reg.

REPEAT

ADS

CNTEN

REPEAT

ADS

CNTEN

ADDR_R

ADDR_L

TDI

TCK

TMS

INTERRUPT

JTAG

COLLISION

DETECTION

LOGIC

CE1

TRST

TDO

CE1

R/W

COL

INT

INT_R

5652 drw 01

(2)

ZZR

CONTROL

LOGIC

NOTES:

1. Address A18 is a NC for the IDT70T3319. Also, Addresses A18 and A17 are NC's for the IDT70T3399.

2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and

OPTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode.

FEBRUARY 2018

DSC-5652/9

12 3 4 5 6 7...27

中文翻译

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与70T3399S200BCGI8相关器件

型号	品牌	获取价格	描述	数据表
70T3399S200BFG	IDT	获取价格	HIGH-SPEED SYNCHRONOUS DUAL-PORT STATIC RAM
70T3399S200BFG8	IDT	获取价格	HIGH-SPEED SYNCHRONOUS DUAL-PORT STATIC RAM
70T3399S200BFGI	IDT	获取价格	HIGH-SPEED SYNCHRONOUS DUAL-PORT STATIC RAM
70T3399S200BFGI8	IDT	获取价格	HIGH-SPEED SYNCHRONOUS DUAL-PORT STATIC RAM
70T34L20BFG	IDT	获取价格	Dual-Port SRAM, 4KX18, 20ns, CMOS, PBGA100, FPBGA-100
70T34L20PFG	IDT	获取价格	Dual-Port SRAM, 4KX18, 20ns, CMOS, PQFP100, PLASTIC, TQFP-100
70T34L25BFG	IDT	获取价格	Dual-Port SRAM, 4KX18, 25ns, CMOS, PBGA100, FPBGA-100
70T34L25BFGI	IDT	获取价格	Dual-Port SRAM, 4KX18, 25ns, CMOS, PBGA100, FPBGA-100
70T34L25PFG	IDT	获取价格	Dual-Port SRAM, 4KX18, 25ns, CMOS, PQFP100, PLASTIC, TQFP-100
70T34L25PFGI	IDT	获取价格	Dual-Port SRAM, 4KX18, 25ns, CMOS, PQFP100, PLASTIC, TQFP-100

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