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709269S12PFGI8 PDF预览

709269S12PFGI8

更新时间: 2024-10-27 20:35:51
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
17页 691K
描述
Dual-Port SRAM

709269S12PFGI8 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:TQFP-100Reach Compliance Code:compliant
HTS代码:8542.32.00.41风险等级:5.84
最长访问时间:12 nsJESD-30 代码:S-PQFP-G100
内存密度:262144 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:16功能数量:1
端子数量:100字数:16384 words
字数代码:16000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:16KX16封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装形状:SQUARE
封装形式:FLATPACK并行/串行:PARALLEL
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子位置:QUAD
Base Number Matches:1

709269S12PFGI8 数据手册

 浏览型号709269S12PFGI8的Datasheet PDF文件第2页浏览型号709269S12PFGI8的Datasheet PDF文件第3页浏览型号709269S12PFGI8的Datasheet PDF文件第4页浏览型号709269S12PFGI8的Datasheet PDF文件第5页浏览型号709269S12PFGI8的Datasheet PDF文件第6页浏览型号709269S12PFGI8的Datasheet PDF文件第7页 
HIGH-SPEED 32/16K x 16  
SYNCHRONOUS  
IDT709279/69S/L  
DUAL-PORT STATIC RAM  
Features  
True Dual-Ported memory cells which allow simultaneous  
access of the same memory location  
High-speed clock to data access  
– Commercial:9/12/15ns(max.)  
– Industrial: 12ns (max.)  
Counter enable and reset features  
Full synchronous operation on both ports  
– 4ns setup to clock and 1ns hold on all control, data, and  
addressinputs  
Data input, address, and control registers  
Low-power operation  
– Fast 9ns clock to data out in the Pipelined output mode  
– Self-timedwriteallowsfastcycletime  
– IDT709279/69S  
Active:950mW(typ.)  
– 15ns cycle time, 67MHz operation in Pipelined output mode  
Separate upper-byte and lower-byte controls for  
multiplexed bus and bus matching compatibility  
TTL- compatible, single 5V (±10%) power supply  
Industrial temperature range (–40°C to +85°C) is  
available for selected speeds  
Standby: 5mW (typ.)  
– IDT709279/69L  
Active:950mW(typ.)  
Standby: 1mW (typ.)  
Flow-Through or Pipelined output mode on either port via  
the FT/PIPE pin  
Available in a 100-pin Thin Quad Flatpack (TQFP) package  
Green parts available. See ordering information  
Dual chip enables allow for depth expansion without  
additionallogic  
FunctionalBlockDiagram  
R/W  
UB  
R
R/W  
L
R
UB  
L
CE0L  
CE1L  
CE0R  
CE1R  
1
0
1
0
0/1  
0/1  
LBR  
LBL  
OE  
R
OE  
L
1a 0a  
1b 0b  
0a 1a  
0b 1b  
0/1  
FT/PIPE  
L
b
a
0/1  
a
b
FT/PIPER  
,
,
I/O8L  
I/O15L  
-
I/O8R-I/O15R  
I/O  
Control  
I/O  
Control  
I/O0L-I/O7L  
I/O0R-I/O7R  
(1)  
(1)  
A
14R  
0R  
A
14L  
Counter/  
Address  
Reg.  
Counter/  
Address  
Reg.  
A
MEMORY  
ARRAY  
A
0L  
CLK  
ADS  
CNTEN  
R
CLK  
L
L
L
R
ADS  
R
CNTEN  
CNTRST  
L
CNTRST  
R
3243 drw 01  
NOTE:  
1. A14X is a NC for IDT709269.  
JUNE 2015  
1
DSC-3243/15  
©2015 Integrated Device Technology, Inc.  

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