Datasheet > 70261S25PFG8

70261S25PFG8

更新时间： 2024-09-19 00:36:19

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
20页	203K
描述
HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM

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中文翻译

获取价格

数据手册

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70261S25PFG8 数据手册

HIGH-SPEED

16K x 16 DUAL-PORT

STATIC RAM WITH INTERRUPT

IDT70261S/L

LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

Features

◆

IDT70261 easily expands data bus width to 32 bits or more

using the Master/Slave select when cascading more than

one device

M/S = H for BUSY output flag on Master,

M/S = L for BUSY input on Slave

Busy and Interrupt Flags

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

◆

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

High-speed access

◆

– Commercial:15/20/25/35/55ns(max.)

– Industrial 20/25ns (max.)

Low-power operation

◆

– IDT70261S

Active:750mW(typ.)

◆

Standby: 5mW (typ.)

– IDT70261L

Active:750mW(typ.)

Standby: 1mW (typ.)

Separate upper-byte and lower-byte control for multiplexed

bus compatibility

Fully asynchronous operation from either port

TTL-compatible, single 5V ( 10%) power supply

Available in 100-pin Thin Quad Flatpack

Industrial temperature range (-40^OC to +85^OC) is available

for selected speeds

◆

Green parts available. See ordering information

Functional Block Diagram

UBR

I/O8L-I/O15L

I/O8R-I/O15R

I/O

Control

I/O0L-I/O7L

(1,2)

I/O0R-I/O7R

(1,2)

BUSY

13L

13R

Address

Decoder

MEMORY

ARRAY

Address

Decoder

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

R/W

SEM

(2)

SEM

(2)

INTR

INTL

M/S

3039 drw 01

NOTES:

1. (MASTER): BUSY is output; (SLAVE): BUSY is input.

2. BUSY and INT outputs are non-tri-stated push-pull.

JUNE 2018

DSC 3039/12

12 3 4 5 6 7...20

中文翻译

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