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7005S25PFG PDF预览

7005S25PFG

更新时间: 2024-11-19 14:14:03
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
21页 358K
描述
Dual-Port SRAM, 8KX8, 25ns, CMOS, PQFP64, 14 X 14 MM, 1.40 MM HEIGHT, GREEN, TQFP-64

7005S25PFG 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:QFP
包装说明:QFP, QFP64,.66SQ,32针数:64
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.07
Is Samacsys:N最长访问时间:25 ns
I/O 类型:COMMONJESD-30 代码:S-PQFP-G64
JESD-609代码:e3内存密度:65536 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:8
湿度敏感等级:3功能数量:1
端口数量:2端子数量:64
字数:8192 words字数代码:8000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:8KX8
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:QFP64,.66SQ,32
封装形状:SQUARE封装形式:FLATPACK
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:5 V认证状态:Not Qualified
最大待机电流:0.015 A最小待机电流:4.5 V
子类别:SRAMs最大压摆率:0.265 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30Base Number Matches:1

7005S25PFG 数据手册

 浏览型号7005S25PFG的Datasheet PDF文件第2页浏览型号7005S25PFG的Datasheet PDF文件第3页浏览型号7005S25PFG的Datasheet PDF文件第4页浏览型号7005S25PFG的Datasheet PDF文件第5页浏览型号7005S25PFG的Datasheet PDF文件第6页浏览型号7005S25PFG的Datasheet PDF文件第7页 
HIGH-SPEED  
IDT7005S/L  
8K x 8 DUAL-PORT  
STATIC RAM  
M/S = H for BUSY output flag on Master,  
M/S = L for BUSY input on Slave  
Interrupt Flag  
On-chip port arbitration logic  
Full on-chip hardware support of semaphore signaling  
between ports  
Fully asynchronous operation from either port  
Devices are capable of withstanding greater than 2001V  
electrostatic discharge  
Battery backup operation—2V data retention  
TTL-compatible, single 5V (±10%) power supply  
Available in 68-pin PGA, quad flatpack, PLCC, and a 64-pin  
thin quad flatpack  
Industrial temperature range (-40°C to +85°C) is available  
for selected speeds  
Green parts available, see ordering information  
Features  
True Dual-Ported memory cells which allow simultaneous  
reads of the same memory location  
High-speed access  
– Military:20/25/35/55/70ns(max.)  
– Industrial: 35/55ns(max.)  
– Commercial:15/17/20/25/35/55ns(max.)  
Low-power operation  
– IDT7005S  
Active:750mW(typ.)  
Standby: 5mW (typ.)  
– IDT7005L  
Active:700mW(typ.)  
Standby: 1mW (typ.)  
IDT7005 easily expands data bus width to 16 bits or more  
using the Master/Slave select when cascading more than  
one device  
FunctionalBlockDiagram  
OE  
R
OE  
CE  
L
L
CER  
R/W  
L
R/WR  
I/O0L- I/O7L  
I/O0R-I/O7R  
I/O  
I/O  
Control  
Control  
BUSY (1,2)  
L
(1,2)  
BUSY  
R
A
12R  
0R  
A
12L  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A
0L  
A
13  
13  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE  
OE  
R/W  
L
CE  
OE  
R/W  
R
L
R
R
L
SEM  
R
SEM  
INTL  
L
M/S  
(2)  
(2)  
INTR  
2738 drw 01  
NOTES:  
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.  
2. BUSY outputs and INT outputs are non-tri-stated push-pull.  
SEPTEMBER 2012  
1
DSC 2738/17  
©2012IntegratedDeviceTechnology,Inc.  

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