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7005L35FG8 PDF预览

7005L35FG8

更新时间: 2024-11-06 11:00:35
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器
页数 文件大小 规格书
21页 358K
描述
Dual-Port SRAM, 8KX8, 35ns, CMOS, PQFP68, 0.970 X 0.970 INCH, 0.080 INCH HEIGHT, GREEN, QFP-68

7005L35FG8 数据手册

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HIGH-SPEED  
IDT7005S/L  
8K x 8 DUAL-PORT  
STATIC RAM  
M/S = H for BUSY output flag on Master,  
M/S = L for BUSY input on Slave  
Interrupt Flag  
On-chip port arbitration logic  
Full on-chip hardware support of semaphore signaling  
between ports  
Fully asynchronous operation from either port  
Devices are capable of withstanding greater than 2001V  
electrostatic discharge  
Battery backup operation—2V data retention  
TTL-compatible, single 5V (±10%) power supply  
Available in 68-pin PGA, quad flatpack, PLCC, and a 64-pin  
thin quad flatpack  
Industrial temperature range (-40°C to +85°C) is available  
for selected speeds  
Green parts available, see ordering information  
Features  
True Dual-Ported memory cells which allow simultaneous  
reads of the same memory location  
High-speed access  
– Military:20/25/35/55/70ns(max.)  
– Industrial: 35/55ns(max.)  
– Commercial:15/17/20/25/35/55ns(max.)  
Low-power operation  
– IDT7005S  
Active:750mW(typ.)  
Standby: 5mW (typ.)  
– IDT7005L  
Active:700mW(typ.)  
Standby: 1mW (typ.)  
IDT7005 easily expands data bus width to 16 bits or more  
using the Master/Slave select when cascading more than  
one device  
FunctionalBlockDiagram  
OE  
R
OE  
CE  
L
L
CER  
R/W  
L
R/WR  
I/O0L- I/O7L  
I/O0R-I/O7R  
I/O  
I/O  
Control  
Control  
BUSY (1,2)  
L
(1,2)  
BUSY  
R
A
12R  
0R  
A
12L  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A
0L  
A
13  
13  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE  
OE  
R/W  
L
CE  
OE  
R/W  
R
L
R
R
L
SEM  
R
SEM  
INTL  
L
M/S  
(2)  
(2)  
INTR  
2738 drw 01  
NOTES:  
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.  
2. BUSY outputs and INT outputs are non-tri-stated push-pull.  
SEPTEMBER 2012  
1
DSC 2738/17  
©2012IntegratedDeviceTechnology,Inc.  

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