Datasheet > 670MI-02LFT

670MI-02LFT

更新时间： 2025-09-22 19:31:39

品牌	Logo	应用领域
瑞萨 - RENESAS		时钟
页数	文件大小	规格书
8页	309K
描述
输入信号类型:时钟;输出信号类型:CMOS;元器件封装:16-SOIC;

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670MI-02LFT 数据手册

DATASHEET

LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER

ICS670-02

Description

Features

The ICS670-02 is a high speed, low phase noise, Zero

Delay Buffer (ZDB) which integrates IDT’s proprietary

analog/digital Phase Locked Loop (PLL) techniques. Part of

• Packaged in 16-pin SOIC

• Pb (lead) free package, RoHS compliant

• Clock inputs from 5 to 160 MHz (see page 2)

• Patented PLL with low phase noise

• Output clocks up to 160 MHz at 3.3 V

• 15 selectable on-chip multipliers

IDT’s ClockBlocks family, the part’s zero delay feature

means that the rising edge of the input clock aligns with the

rising edges of the outputs giving the appearance of no

delay through the device. There are two identical outputs on

the chip. The FBCLK should be used to connect to the

FBIN. Each output has its own output enable pin.

• Power down mode available

• Low phase noise: -111 dBc/Hz at 10 kHz

• Output enable function tri-states outputs

• Low jitter 15 ps one sigma

• Advanced, low power, sub-micron CMOS process

• Operating voltage of 3.3 V or 5 V

The ICS670-02 is ideal for synchronizing outputs in a large

variety of systems, from personal computers to data

communications to video. By allowing off-chip feedback

paths, the chip can eliminate the delay through other

devices. The 15 different on-chip multipliers work in a

variety of applications. For other multipliers, including

functional multipliers, see the ICS527.

• Industrial temperature range available (-40 to +85°C)

Block Diagram

VDD

OE1

Voltage

Controlled

Oscillator

ICLK

FBCLK

Phase

Detector,

Charge

Pump, and

Loop Filter

Divide by

FBIN

CLK2

S3:S0

GND

External Feedback from FBCLK is recommended.

OE2

IDT™ / ICS™ LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER 1

ICS670-02

REV J 051310

12 3 4 5 6 7 8

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