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667M-01 PDF预览

667M-01

更新时间: 2024-09-17 20:59:39
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
6页 170K
描述
Clock Generator, 74.17582418MHz, CMOS, PDSO8, 0.150 INCH, SOIC-8

667M-01 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:0.150 INCH, SOIC-8
针数:8Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.82JESD-30 代码:R-PDSO-G8
JESD-609代码:e0长度:4.9 mm
湿度敏感等级:1端子数量:8
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:74.17582418 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
电源:3.3 V主时钟/晶体标称频率:27 MHz
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Clock Generators最大供电电压:3.465 V
最小供电电压:3.15 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:3.9 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

667M-01 数据手册

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DATASHEET  
HDTV CLOCK SYNTHESIZER  
ICS667-01  
Description  
Features  
The ICS667-01 is a low-cost, low jitter, high-performance  
PLL clock synthesizer designed to produce the 74.176 MHz  
clock necessary for HDTV systems. Using IDT’s patented  
analog Phase-Locked Loop (PLL) techniques, the device  
accepts a 27 MHz crystal or clock input. The zero ppm  
synthesis error exactly locks the display to the digital  
stream.  
Packaged in 8-pin SOIC  
Available in Pb (lead) free package  
Input frequency of 27 MHz  
Zero ppm synthesis error in output clock  
3.3 V ±±5 operating supply  
Ideal for HDTV applications and oscillator manufacturers  
Advanced, low power, sub-micron CMOS process  
NOTE: EOL for non-green parts to occur on 5/13/10  
per PDN U-09-01  
IDT manufactures the largest variety multimedia clock  
synthesizers for all applications. Consult IDT to eliminate  
crystals and oscillators from your board.  
Block Diagram  
VDD  
OE  
Clock  
Synthesis  
and Control  
Circuitry  
CLK  
74.17582418 MHz  
ICLK/X1  
X2  
27 MHz  
crystal or  
clock input  
Clock  
Buffer  
27.0000 MHz  
2
GND  
Optional tuning crystal capacitors  
IDT™ / ICS™ HDTV CLOCK SYNTHESIZER  
1
ICS667-01  
REV D 110409  

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