Datasheet > 638E17003A3T

638E17003A3T

更新时间： 2023-01-03 01:40:36

品牌	Logo	应用领域
西迪斯 - CTS		/
页数	文件大小	规格书
7页	707K
描述
LVPECL Output Clock Oscillator

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数据手册

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638E17003A3T 数据手册

Model 638

Ultra Low Jitter LVPECL or LVDS Clock

Features

. Ceramic Surface Mount Package

. Ultra Low Phase Jitter Performance, 100fs Typical

. Fundamental or 3^rdOvertone Crystal Design

. Frequency Range 80 – 170MHz *

. +2.5V or +3.3V Operation

Part Dimensions:

7.0 × 5.0 × 2.0mm • 178.462mg

. Output Enable Standard

. Tape and Reel Packaging, EIA‐418

Standard Frequencies, 100fs Maximum

‐ 125.00MHz

‐ 155.52MHz

‐ 156.25MHz

‐ 161.1328MHz

Applications

. SerDes

. PON

. Ethernet/GbE/SyncE

. Fiber Channel

* Check with factory for availability.

. Storage Area Networking

. Broadband Access

. SONET/SDH/DWDM

. Test and Measurement

Description

CTS Model 638 is a low cost, high performance clock oscillator supporting differential LVPECL or LVDS outputs.

Employing the latest IC technology, M638 has excellent stability and low jitter/phase noise performance.

Ordering Information

Frequency

Stability

Temperature

Supply

Voltage

Frequency Code

[MHz]

Output Type

Packaging

Model

Range

638

XXX or XXXX

Output

Stability

Voltage

+2.5Vdc

+3.3Vdc

Code

±20ppm ²

±25ppm

±50ppm

±100ppm

LVPECL ‐ Pin 1 Enable

LVDS ‐ Pin 1 Enable

LVPECL ‐ Pin 2 Enable

LVDS ‐ Pin 2 Enable

Frequency

Product Frequency Code ¹

Temp. Range

‐10°C to +60°C

‐20°C to +70°C

‐40°C to +85°C

Packing

1k pcs./reel

Code

Notes:

1] Refer to document 016‐1454‐0, Frequency Code Tables. 3‐digits for frequencies <100MHz, 4‐digits for frequencies 100MHz or greater.

Consult factory for availability of 6I Stability/Temperature combination.

Not all performance combinations and frequencies may be available.

Contact your local CTS Representative or CTS Customer Service for availability.

DOC# 008‐0539‐0 Rev. A

Page 1 of 7

equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.

12 3 4 5 6 7

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