Datasheet > 621S

621S

更新时间： 2023-12-20 18:44:59

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621S 数据手册

Low Skew 1 to 4 Clock Buffer

621S

DATASHEET

Description

Features

The 621S is a low cost, high-speed single input to four output

clock buffer. The 621S has best in class Additive Phase Jitter

of sub 50fsec.

• Low additive phase jitter RMS: 50fs

• Extremely low skew outputs (50ps)

• Low cost clock buffer

IDT makes many non-PLL and PLL based low skew output

devices as well as Zero Delay Buffers to synchronize clocks.

Contact IDT for all of your clocking needs.

• Packaged in 8-pin SOIC and 8-pin DFN, Pb-free

• Input/Output clock frequency up to 200 MHz

• Non-inverting output clock

• Ideal for networking clocks

• Operating Voltages: 1.8V to 3.3V

• Output Enable mode tri-states outputs

• Advanced, low power CMOS process

• Extended temperature range (-40°C to +105°C)

Block Diagram

ICLK

Output Enable

621S REVISION A 03/18/15

12 3 4 5 6 7...13

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