Datasheet > 601R-25ILF

601R-25ILF

更新时间： 2024-11-27 07:59:59

品牌	Logo	应用领域
矽成 - ICSI		时钟
页数	文件大小	规格书
5页	141K
描述
LOW PHASE NOISE 1 TO 5 CLOCK MULTIPLIER

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601R-25ILF 数据手册

ICS601-25

LOW PHASE NOISE 1 TO 5 CLOCK MULTIPLIER

Description

Features

The ICS601-25 is a low-cost, low phase noise, high

performance clock synthesizer for applications which

require low phase noise, low jitter, and low skew fanout.

It is ICS’ lowest phase noise multiplier, and also the

lowest CMOS part in the industry. Using ICS’ patented

analong and digital Phase Locked Loop (PLL)

• Packaged in 20-pin SSOP

• Uses fundamental 10 - 27 MHz crystal or clock

• Output clocks up to 156 MHz

• Low phase noise: -132 dBc/Hz at 10 kHz

• Five low skew (<250 ps) outputs

techniques, the chip accepts a 10-27 MHz crystal or

clock input, and produces output clocks up to 156 MHz.

• Low jitter - 18 ps one sigma at 125 MHz

• Full swing CMOS outputs with 25 mA drive capability

at TTL levels

• Powerdown mode lowers power consumption

• Advanced, low power, sub-micron CMOS process

• Industrial temperature version available

• Available in Pb (lead) free package

• Operating voltage of 3.3 V

Block Diagram

VDD

Reference

Divider

Phase

Comparator

Charge

Pump

Loop

Filter

VCO

CLK1

CLK2

CLK3

CLK4

CLK5

X1/ICLK

VCO

Divide

Crystal

Oscillator

Crystal or

clock input

ROM Based

Multipliers

GND

S3:0

MDS 601-25 C

Revision 071505

Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

12 3 4 5

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