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5T929-10NLI PDF预览

5T929-10NLI

更新时间: 2024-11-21 20:10:59
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
9页 306K
描述
PLL Based Clock Driver, 5T Series, 2 True Output(s), 0 Inverted Output(s), PQCC28, PLASTIC, VFQFN-28

5T929-10NLI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFN
包装说明:HVQCCN, LCC28,.24SQ,25针数:28
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.88
系列:5T输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-PQCC-N28JESD-609代码:e0
长度:6 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:28
实输出次数:2最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:HVQCCN封装等效代码:LCC28,.24SQ,25
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):225电源:2.5/3.3 V
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.02 ns
座面最大高度:1 mm子类别:Clock Driver
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):2.375 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:NO LEAD
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:6 mm
最小 fmax:666.52 MHzBase Number Matches:1

5T929-10NLI 数据手册

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IDT5T929  
PRECISION CLOCK GENERATOR  
OC-48 APPLICATIONS  
FEATURES:  
DESCRIPTION:  
Input frequency:  
The IDT5T929 generates a high precision FEC (Forward Error Cor-  
rection) or non-FEC source clock for SONET/SDH systems as well as a  
source clock for Gigabit Ethernet systems. This device also has clock  
regeneration capability: it creates a "clean" version of the clock input by  
using the internal oscillator to square the input clock's rising and falling  
edges and remove jitter. In the event that the main clock input fails, the  
device automatically locks to a backup reference clock using a hitless  
switchover mechanism.  
- ForSONETnon-FEC:19.44MHz,38.88MHz,77.76MHz,155.52MHz,  
311.04MHz, or 622.08MHz  
- For SONET FEC: 20.83MHz, 41.66MHz, 83.31MHz, 166.63MHz,  
333.26MHz, or 666.52MHz  
- For 10GE copper: 19.53MHz, 39.06MHz, 78.125MHz, 156.25MHz,  
312.5MHz, or 625MHz  
- For 10GE optical: 20.14MHz, 40.28MHz, 80.56MHz, 161.13MHz,  
322.26MHz, or 644.53MHz  
• Output frequency range selection  
• 1x, 2x, 4x, 8x, 16x, and 32x outputs on QOUT  
• Regenerated input clock on QREG  
Lock indicator  
• Power-down mode  
LVPECL or LVDS outputs  
This device detects loss ofvalidCLKINandleaves the VCOofthe PLLat  
thelastvalidfrequencywhileanalternateinputREFINis selected. IfCLKIN  
andREFINaredifferentfrequencies,themultiplicationfactorwillbeadjustedto  
retainthesameoutputfrequency.  
TheIDT5T929canactasatranslatorfromadifferentialLVPECL,LVDS,or  
single-ended LVTTL input to LVPECL or LVDS outputs. The IDT5T929-10  
has LVDSoutputs andthe IDT5T929-30has LVPECLoutputs.  
ThetwomodesofoutputfrequencyrangearecontrolledbytheSELmode.  
WhenSELmodeishighorlow,theQOUTisamultipliedversionoftheinputclock  
while QREG is a regeneratedversionofthe inputclock.  
Two modes of output frequency range  
- Mode0:QOUT range155.5-166.6MHz. QREG isaregeneratedversion  
ofthe inputclock.  
- Mode 1: QOUT range 622 - 666.5MHz. QREG is a regenerated version  
ofthe inputclockfrequency.  
Hitless switchover  
Differential LVPECL, LVDS, or single-ended LVTTL input interface  
• 2.375 - 3.465V core and I/O  
Available in VFQFPN package  
APPLICATIONS:  
Terabit routers  
• Gigabit ethernet systems  
• SONET / SDH systems  
Digital cross connects  
• Optical transceiver modules  
FUNCTIONALBLOCKDIAGRAM  
QREG  
CLKIN  
CLKIN  
INPUT  
MUX  
DIVN  
QREG  
PLL  
QOUT  
QOUT  
DIVM  
CONTROL  
LOGIC  
LOCK,  
FREQ.  
DETECTOR  
REFIN  
REFIN  
PD  
SELMODE  
LOCK  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
OCTOBER 2008  
1
c
2004 Integrated Device Technology, Inc.  
DSC 6400/17  

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