Datasheet > 5PB1102

5PB1102

更新时间： 2023-12-20 18:45:07

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
40页	1786K
描述
1.8V to 3.3V 1:2 LVCMOS High Performance Clock Buffer

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数据手册

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5PB1102 数据手册

1.8V to 3.3V High-Performance

LVCMOS Clock Buffer Family

5PB11xx

Datasheet

Description

The 5PB11xx is a high-performance LVCMOS clock buffer family

Features

▪ High-performance 1:2, 1:4, 1:6, 1:8, 1:10 LVCMOS clock buffer

▪ Very low pin-to-pin skew: < 50ps

▪ Very low additive jitter: < 50fs

of devices. It has an additive phase jitter of 50fs RMS.

There are five different fan-out variations available: 1:2 to 1:10.

▪ Supply voltage: 1.8V to 3.3V

The 5PB11xx supports a synchronous glitch-free output enable

(OE) function to eliminate any potential intermediate incorrect

output clock cycles when enabling or disabling outputs. It can

operate from a 1.8V to 3.3V supply.

▪ 3.3V tolerant input clock

▪ f_MAX= 200MHz

▪ Integrated serial termination for 50Ω channel

▪ Packaged in 8-, 14-, 16-, 20-pin TSSOP and as small as

2.0 × 2.0 mm DFN and 3.0 × 3.0 mm VFQFPN packages

Typical Applications

▪ Industrial (-40°C to +85°C) and extended (-40°C to +105°C)

temperature ranges

▪ Industrial applications

▪ Automotive:

▪ 5PB1104 available in AEC-Q100 qualified, Automotive Grade 1

(-40°C to +125°C)

• Radar, Lidar, and other applications

▪ 5PB1110 available in AEC-Q100 qualified, Automotive Grade 2

(-40°C to +105°C)

Block Diagram

LVCMOS

CLKIN

LVCMOS

September 15, 2023

12 3 4 5 6 7...40

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