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5P49V6968

更新时间: 2023-12-20 18:46:07
品牌 Logo 应用领域
瑞萨 - RENESAS /
页数 文件大小 规格书
33页 1401K
描述
VersaClock? 6E Programmable Clock Generator with 8 Additional Output Copies

5P49V6968 数据手册

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®
VersaClock 6E Programmable  
5P49V6968  
Clock Generator  
Datasheet  
Description  
Features  
The 5P49V6968 is a programmable clock generator that is  
intended for high-performance consumer, networking, industrial,  
computing, and data communications applications. This is  
Renesas’ sixth generation of programmable clock technology  
(VersaClock 6E).  
.
.
Flexible 1.8V, 2.5V, and 3.3V power rails  
High-performance, low phase noise PLL, < 0.5ps RMS typical  
phase jitter on outputs  
.
.
Four banks of internal OTP memory  
• In-system or factory programmable  
I2C serial programming interface  
The 5P49V6968 generates the frequencies from a single  
reference clock, which can originate from one of the two  
redundant clock inputs. A glitchless manual switchover function  
allows one of the redundant clocks to be selected during normal  
operation.  
• 0xD0 or 0xD4 I2C address options allow multiple devices to  
be configured in a same system  
.
.
Reference LVCMOS output clock  
Three universal configurable outputs (OUT1, 2, 4):  
• Differential (LVPECL, LVDS, or HCSL) 1kHz to 350MHz  
Two select pins allow up to four different configurations to be  
programmed, and can be used for different operating modes.  
• Two single-ended (in-phase or 180 degrees out of phase)  
1kHz to 200MHz  
Typical Applications  
• I/O VDDs can be mixed and matched, supporting 1.8V  
(LVDS and LVCMOS), 2.5V, or 3.3V  
.
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.
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Ethernet switch/router  
PCI Express 1.0/2.0/3.0/4.0 spread spectrum on  
PCI Express 1.0/2.0/3.0/4.0/5.0 spread spectrum off  
Broadcast video/audio timing  
Multi-function printer  
• Independent spread spectrum on each output pair  
Eight additional LPHCSL outputs (OUT 3, 5–11)  
• 1.8V low power supply  
.
• 1kHz to 200MHz  
Processor and FPGA clocking  
Any-frequency clock conversion  
MSAN/DSLAM/PON  
.
.
.
.
Programmable output enable or power-down mode  
Redundant clock inputs with manual switchover  
Available in 6 × 6 mm 48-VFQFPN package  
-40° to +85°C industrial temperature operation  
Fiber Channel, SAN  
Telecom line cards  
Datacenter  
Block Diagram  
VDDO  
OUT0_SEL_I2CB  
VDDO  
0
XIN/REF  
XOUT  
1
OUT1  
FOD1  
FOD2  
FOD3  
OUT1B  
VDDO  
2
CLKSEL  
OUT2  
SD/OE  
SEL1/SDA  
SEL0/SCL  
OTP  
and  
Control  
Logic  
OUT2B  
PLL  
OEA  
VDDA  
VDDD  
OUT3, 5, 6, 11  
OEB  
OUT7, 8, 9, 10  
VDDO  
4
OUT4  
FOD4  
OUT4B  
© 2020 Renesas Electronics Corporation  
1
August 20, 2020  

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