Datasheet > 5L35023

5L35023

更新时间： 2023-12-20 18:45:53

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
39页	930K
描述
VersaClock? 3S Programmable Clock Generator

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中文翻译

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数据手册

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5L35023 数据手册

VersaClock^®3S Programmable

Clock Generator

5L35023

Datasheet

Description

Features

The 5L35023 is a member of the VersaClock^®3S programmable

clock generator family with 1.8V operation voltage, and is

designed for industrial, consumer, and PCI Express applications.

The device features a 3 PLL architecture design; each PLL is

individually programmable and allowing up to 6 unique frequency

outputs.

▪ Configurable OE pin function as OE, PD#, PPS or DFC control

function

▪ Configurable PLL bandwidth; minimizes jitter peaking

▪ PPS: Proactive Power Saving features save power during the

end device power down mode

▪ PPB: Performance Power Balancing feature allows minimum

power consumption based on required performance

The 5L35023 has built-in features such as Proactive Power

Saving (PPS), Performance-Power Balancing (PPB), Overshoot

Reduction Technology (ORT) and extreme low power DCO. An

internal OTP memory allows the user to store the configuration in

the device without programming after power-up, then program the

5L35023 again through the I²C interface.

▪ DFC: Dynamic Frequency Control feature allows user to

dynamically switch between and up to 4 different frequencies

smoothly

▪ Spread spectrum clock to lower system EMI

▪ I²C interface

The device has programmable VCO and PLL source selection,

allowing power-performance optimization based on the application

requirements.

▪ Suspend Mode, featuring RTC clock only when system goes

into low-power operation modes

Output Features

Typical Applications

▪ 2 DIFF outputs with configurable LPHSCL, LVCMOS output

pairs: 1MHz–125MHz

▪ Embedded computing devices

▪ Consumer application crystal oscillator replacements

▪ SmartDevice, Handheld, and Consumer applications

▪ 3 LVCMOS outputs: 1MHz–125MHz

▪ LVPECL, LVDS, CML and SSTL logic can be easily supported

with the LP-HCSL outputs. See application note AN-891 for

alternate terminations

Key Specifications

▪ PCIe Gen1/2/3 compliant

▪ Maximum of 8 LVCMOS outputs

▪ Typical 1.5ps rms jitter integer range: 12kHz–20MHz

▪ Typical ultra-power-down current 50μA

▪ < 2μA RTC clock in Suspend Mode operation

▪ Low-power 32.768kHz clock supported for all SE1–SE3

Block Diagram

CLKIN/X1

OSC

REF

VDDDIFF1

DIFF1

DIFF1B

Programmable

Load Capacitor

PLL1

VDDDIFF2

DIFF2

DIFF2B

SEL_DFC/ SCL_DFC1

SDA_DFC0

VDDSE1

SE1

Mux

PLL2

Divider

OE1

Calibration

VDDSE2

SE2

PLL3

VDD18

OE2

32.768K

VDDA

DCO

VDDSE3

SE3

VBAT

OE3

November 30, 2022

12 3 4 5 6 7...39

中文翻译

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