Datasheet > 5962R9858002QXC

5962R9858002QXC

更新时间： 2024-01-28 06:23:47

品牌	Logo	应用领域
艾法斯 - AEROFLEX		/
页数	文件大小	规格书
14页	103K
描述
RadHard Schmitt CMOS 16-bit Bidirectional MultiPurpose Transceiver

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5962R9858002QXC 技术参数

生命周期：	Active	零件包装代码：	DFP
包装说明：	DFP,	针数：	48
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.3	其他特性：	ALSO OPERATES ON SUPPLY VOLTAGE RANGE 4.5V TO 5.5 V
系列：	AC	JESD-30 代码：	R-XDFP-F48
JESD-609代码：	e4	长度：	15.875 mm
逻辑集成电路类型：	BUS TRANSCEIVER	位数：	8
功能数量：	2	端口数量：	2
端子数量：	48	最高工作温度：	125 °C
最低工作温度：	-55 °C	输出特性：	3-STATE
输出极性：	TRUE	封装主体材料：	UNSPECIFIED
封装代码：	DFP	封装形状：	RECTANGULAR
封装形式：	FLATPACK	传播延迟（tpd）：	20 ns
认证状态：	Qualified	筛选级别：	MIL-PRF-38535 Class V
座面最大高度：	3.048 mm	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	MILITARY	端子面层：	GOLD
端子形式：	FLAT	端子节距：	0.635 mm
端子位置：	DUAL	总剂量：	100k Rad(Si) V
宽度：	9.652 mm

5962R9858002QXC 数据手册

UT54ACS164245S

RadHard Schmitt CMOS 16-bit Bidirectional MultiPurpose Transceiver

Datasheet

April, 2002

LOGIC SYMBOL

FEATURES

OE1 (48)

· Voltage translation

(24)

OE2 (25)

2EN1 (BA)

2EN2 (AB)

DIR2

1B1

- 5V bus to 3.3V bus

- 3.3V bus to 5V bus

(1)

DIR1

1A1

1EN1 (BA)

1EN2 (AB)

· Cold sparing

(2)

(47)

- 1MW minimum input impedance power-off

· 0.6mm Commercial RadHard^TMCMOS

- Total dose: 100K rad(Si)

- Single Event Latchup immune

· High speed, low power consumption

(46)

(44)

(3)

(5)

(6)

(8)

1A2

1A3

1B2

1B3

1B4

1B5

(43)

(41)

(40)

(38)

1A4

1A5

· Schmitt trigger inputs to filter noisy signals

· Available QML Q or V processes

· Standard Microcircuit Drawing 5962-98580

(9)

(11)

(12)

(13)

1A6

1A7

1A8

2A1

1B6

1B7

(37)

(36)

1B8

2B1

· Package:

- 48-lead flatpack, 25 mil pitch (.390 x .640)

(35)

(33)

(32)

(30)

(29)

(27)

(26)

(14)

(16)

(17)

2B2

2B3

2B4

2B5

2A2

2A3

DESCRIPTION

The 16-bit wide UT54ACS164245S MultiPurpose transceiver

2A4

2A5

is built using UTMC’s Commercial RadHard^TMepitaxial

CMOS technology and is ideal for space applications. This high

speed, low power UT54ACS164245S transceiver is designed to

perform multiple functions including: asynchronous two-way

communication, signal buffering, voltage translation, and cold

sparing. With V_DDequal to zero volts, the UT54ACS164245S

(19)

(20)

(22)

(23)

2B6

2B7

2A6

2A7

2A8

2B8

PIN DESCRIPTION

outputs and inputs present a minimum impedance of 1MW mak-

ing it ideal for "cold spare" applications. Balanced outputs and

low "on" output impedance make the UT54ACS164245S well

suited for driving high capacitance loads and low impedance

backplanes. The UT54ACS164245S enables system designers

to interface 3.3 volt CMOS compatible components with 5 volt

CMOS components. For voltage translation, the A port inter-

faces with the 3.3 volt bus; the B port interfaces with the 5 volt

bus. The direction control (DIRx) controls the direction of data

flow. The output enable (OEx) overrides the direction control

and disables both ports. These signals can be driven from either

port A or B. The direction and output enable controls operate

these devices as either two independent 8-bit transceivers or one

16-bit transceiver.

Pin Names

Description

OEx

DIRx

xAx

Output Enable Input (Active Low)

Direction Control Inputs

Side A Inputs or 3-State Outputs (3.3V Port)

Side B Inputs or 3-State Outputs (5V Port)

xBx

FUNCTION TABLE

ENABLE

OEx

DIRECTION

DIRx

OPERATION

B Data To A Bus

A Data To B Bus

Isolation

12 3 4 5 6 7...14

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